riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Give TileLink IDs more sensible names

Browse Source 
* Outermost -> MCtoEdge
 * MMIO_Outermost -> MMIOtoEdge

Then the corresponding parameters objects are

 * L1toL2 -> innerParams
 * L2toMC -> outerMemParams
 * L2toMMIO -> outerMMIOParams
 * MCtoEdge -> edgeMemParams
 * MMIOtoEdge -> edgeMMIOParams
This commit is contained in:
Howard Mao
2016-09-27 11:44:11 -07:00
committed by Henry Cook
parent 8a55521b01
commit 7d6fb950b6
4 changed files with 12 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/groundtest/NastiTest.scala
View File

@ -115,7 +115,7 @@ class NastiConverterTest(implicit p: Parameters) extends GroundTest()(p)
val test = Module(new NastiGenerator(genId))
val converter = Module(new TileLinkIONastiIOConverter()(
p.alterPartial { case TLId => "Outermost" }))
p.alterPartial { case TLId => "MCtoEdge" }))
converter.io.nasti <> test.io.mem
TileLinkWidthAdapter(io.mem.head, converter.io.tl)