riscv/rocket-chip
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Queue: silence some warnings

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Wesley W. Terpstra 2017-11-13 17:32:54 -08:00
parent 147fad6387
commit 7cfb69e2d5
2 changed files with 3 additions and 3 deletions
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4
src/main/scala/amba/axi4/Deinterleaver.scala
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@ -40,9 +40,9 @@ class AXI4Deinterleaver(maxReadBytes: Int)(implicit p: Parameters) extends LazyM
val qs = Seq.tabulate(endId) { i => val qs = Seq.tabulate(endId) { i =>
val depth = edgeOut.master.masters.find(_.id.contains(i)).flatMap(_.maxFlight).getOrElse(0) val depth = edgeOut.master.masters.find(_.id.contains(i)).flatMap(_.maxFlight).getOrElse(0)
if (depth > 0) { if (depth > 0) {
Module(new Queue(out.r.bits, beats)).io Module(new Queue(out.r.bits.cloneType, beats)).io
} else { } else {
Wire(new QueueIO(out.r.bits, beats)) Wire(new QueueIO(out.r.bits.cloneType, beats))
} }
} }

2
src/main/scala/rocket/DCache.scala
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@ -99,7 +99,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
val (tl_out_c, release_queue_empty) = val (tl_out_c, release_queue_empty) =
if (cacheParams.acquireBeforeRelease) { if (cacheParams.acquireBeforeRelease) {
val q = Module(new Queue(tl_out.c.bits, cacheDataBeats, flow = true)) val q = Module(new Queue(tl_out.c.bits.cloneType, cacheDataBeats, flow = true))
tl_out.c <> q.io.deq tl_out.c <> q.io.deq
(q.io.enq, q.io.count === 0) (q.io.enq, q.io.count === 0)
} else { } else {