riscv/rocket-chip
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Queue: silence some warnings

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This commit is contained in:
Wesley W. Terpstra
2017-11-13 17:32:54 -08:00
parent 147fad6387
commit 7cfb69e2d5
2 changed files with 3 additions and 3 deletions
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2
src/main/scala/rocket/DCache.scala
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@@ -99,7 +99,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
val (tl_out_c, release_queue_empty) =
if (cacheParams.acquireBeforeRelease) {
val q = Module(new Queue(tl_out.c.bits, cacheDataBeats, flow = true))
val q = Module(new Queue(tl_out.c.bits.cloneType, cacheDataBeats, flow = true))
tl_out.c <> q.io.deq
(q.io.enq, q.io.count === 0)
} else {