diplomacy: define only primary node types
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@ -3,9 +3,11 @@
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package freechips.rocketchip.amba
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package freechips.rocketchip.amba
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import Chisel._
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import Chisel._
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import freechips.rocketchip.diplomacy.OutwardNodeHandle
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import freechips.rocketchip.diplomacy._
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package object ahb
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package object ahb
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{
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{
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type AHBOutwardNode = OutwardNodeHandle[AHBMasterPortParameters, AHBSlavePortParameters, AHBBundle]
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type AHBOutwardNode = OutwardNodeHandle[AHBMasterPortParameters, AHBSlavePortParameters, AHBBundle]
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type AHBInwardNode = InwardNodeHandle[AHBMasterPortParameters, AHBSlavePortParameters, AHBBundle]
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type AHBNode = SimpleNodeHandle[AHBMasterPortParameters, AHBSlavePortParameters, AHBBundle]
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}
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}
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@ -3,9 +3,11 @@
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package freechips.rocketchip.amba
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package freechips.rocketchip.amba
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import Chisel._
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import Chisel._
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import freechips.rocketchip.diplomacy.OutwardNodeHandle
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import freechips.rocketchip.diplomacy._
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package object apb
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package object apb
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{
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{
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type APBOutwardNode = OutwardNodeHandle[APBMasterPortParameters, APBSlavePortParameters, APBBundle]
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type APBOutwardNode = OutwardNodeHandle[APBMasterPortParameters, APBSlavePortParameters, APBBundle]
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type APBInwardNode = InwardNodeHandle[APBMasterPortParameters, APBSlavePortParameters, APBBundle]
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type APBNode = SimpleNodeHandle[APBMasterPortParameters, APBSlavePortParameters, APBBundle]
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}
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}
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@ -7,7 +7,7 @@ import freechips.rocketchip.diplomacy._
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package object axi4
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package object axi4
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{
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{
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type AXI4Node = SimpleNodeHandle[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle]
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type AXI4OutwardNode = OutwardNodeHandle[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle]
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type AXI4OutwardNode = OutwardNodeHandle[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle]
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type AXI4AsyncOutwardNode = OutwardNodeHandle[AXI4AsyncMasterPortParameters, AXI4AsyncSlavePortParameters, AXI4AsyncBundle]
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type AXI4InwardNode = InwardNodeHandle[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle]
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type AXI4Node = NodeHandle[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle, AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle]
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}
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}
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@ -7,6 +7,8 @@ import freechips.rocketchip.config.Parameters
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package object diplomacy
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package object diplomacy
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{
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{
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type SimpleNodeHandle[D, U, B <: Chisel.Data] = NodeHandle[D, U, B, D, U, B]
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def sourceLine(sourceInfo: SourceInfo, prefix: String = " (", suffix: String = ")") = sourceInfo match {
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def sourceLine(sourceInfo: SourceInfo, prefix: String = " (", suffix: String = ")") = sourceInfo match {
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case SourceLine(filename, line, col) => s"$prefix$filename:$line:$col$suffix"
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case SourceLine(filename, line, col) => s"$prefix$filename:$line:$col$suffix"
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case _ => ""
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case _ => ""
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@ -9,7 +9,5 @@ package object interrupts
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{
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{
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type IntInwardNode = InwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]
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type IntInwardNode = InwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]
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type IntOutwardNode = OutwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]
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type IntOutwardNode = OutwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]
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type IntNode = NodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool], IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]
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type IntNode = SimpleNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]
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type IntSyncInwardNode = InwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, SyncInterrupts]
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type IntSyncOutwardNode = OutwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, SyncInterrupts]
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}
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}
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@ -60,8 +60,8 @@ class RoCCCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
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abstract class LazyRoCC(implicit p: Parameters) extends LazyModule {
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abstract class LazyRoCC(implicit p: Parameters) extends LazyModule {
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val module: LazyRoCCModule
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val module: LazyRoCCModule
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val atlNode: TLMixedNode = TLIdentityNode()
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val atlNode: TLNode = TLIdentityNode()
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val tlNode: TLMixedNode = TLIdentityNode()
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val tlNode: TLNode = TLIdentityNode()
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}
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}
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class RoCCIO(outer: LazyRoCC)(implicit p: Parameters) extends RoCCCoreIO()(p) {
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class RoCCIO(outer: LazyRoCC)(implicit p: Parameters) extends RoCCCoreIO()(p) {
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@ -9,11 +9,5 @@ package object tilelink
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{
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{
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type TLInwardNode = InwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle]
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type TLInwardNode = InwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle]
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type TLOutwardNode = OutwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle]
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type TLOutwardNode = OutwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle]
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type TLNode = NodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle, TLClientPortParameters, TLManagerPortParameters, TLBundle]
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type TLNode = SimpleNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle]
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type TLAsyncInwardNode = InwardNodeHandle[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]
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type TLAsyncOutwardNode = OutwardNodeHandle[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]
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type TLRationalInwardNode = InwardNodeHandle[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]
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type TLRationalOutwardNode = OutwardNodeHandle[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]
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type TLMixedNode = MixedNode[TLClientPortParameters, TLManagerPortParameters, TLEdgeIn, TLBundle,
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TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLBundle]
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}
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}
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