riscv/rocket-chip
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clean up WideCounter implementation

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This commit is contained in:
Andrew Waterman 2016-07-15 00:51:01 -07:00
parent d78f1aacd0
commit 7cf44f9b25
1 changed files with 6 additions and 11 deletions
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17
rocket/src/main/scala/util.scala
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@ -138,28 +138,23 @@ object Split
// a counter that clock gates most of its MSBs using the LSB carry-out // a counter that clock gates most of its MSBs using the LSB carry-out
case class WideCounter(width: Int, inc: UInt = UInt(1)) case class WideCounter(width: Int, inc: UInt = UInt(1))
{ {
require(inc.getWidth > 0)
private val isWide = width > 2*inc.getWidth private val isWide = width > 2*inc.getWidth
private val smallWidth = if (isWide) inc.getWidth max log2Up(width) else width private val smallWidth = if (isWide) inc.getWidth max log2Up(width) else width
private val small = Reg(init=UInt(0, smallWidth)) private val small = Reg(init=UInt(0, smallWidth))
private val doInc = inc.orR private val nextSmall = small +& inc
private val nextSmall = small := nextSmall
if (inc.getWidth == 1) small + UInt(1, smallWidth+1)
else Cat(UInt(0,1), small) + inc
when (doInc) { small := nextSmall(smallWidth-1,0) }
private val large = if (isWide) { private val large = if (isWide) {
val r = Reg(init=UInt(0, width - smallWidth)) val r = Reg(init=UInt(0, width - smallWidth))
when (doInc && nextSmall(smallWidth)) { r := r + UInt(1) } when (nextSmall(smallWidth)) { r := r + UInt(1) }
r r
} else null } else null
val value = Cat(large, small) val value = if (isWide) Cat(large, small) else small
def := (x: UInt) = { def := (x: UInt) = {
val w = x.getWidth small := x
small := x(w.min(smallWidth)-1,0) if (isWide) large := x >> smallWidth
if (isWide) large := (if (w < smallWidth) UInt(0) else x(w.min(width)-1,smallWidth))
} }
} }