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tilelink: AtomicAutomata; add errors to the unit test

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This commit is contained in:
Wesley W. Terpstra 2017-11-06 12:05:44 -08:00
parent 88234ead0d
commit 7cc7cd5992
1 changed files with 12 additions and 2 deletions
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14
src/main/scala/tilelink/AtomicAutomata.scala
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@ -281,18 +281,28 @@ object TLAtomicAutomata
/** Synthesizeable unit tests */ /** Synthesizeable unit tests */
import freechips.rocketchip.unittest._ import freechips.rocketchip.unittest._
//TODO ensure handler will pass through operations to clients that can handle them themselves
class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule { class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns)) val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("AtomicAutomata")) val model = LazyModule(new TLRAMModel("AtomicAutomata"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
// Confirm that the AtomicAutomata combines read + write errors
import TLMessages._
val test = new RequestPattern({a: TLBundleA =>
val doesA = a.opcode === ArithmeticData || a.opcode === LogicalData
val doesR = a.opcode === Get || doesA
val doesW = a.opcode === PutFullData || a.opcode === PutPartialData || doesA
(doesR && RequestPattern.overlaps(Seq(AddressSet(0x08, ~0x08)))(a)) ||
(doesW && RequestPattern.overlaps(Seq(AddressSet(0x10, ~0x10)))(a))
})
(ram.node (ram.node
:= TLErrorEvaluator(test)
:= TLFragmenter(4, 256) := TLFragmenter(4, 256)
:= TLDelayer(0.1) := TLDelayer(0.1)
:= TLAtomicAutomata() := TLAtomicAutomata()
:= TLDelayer(0.1) := TLDelayer(0.1)
:= TLErrorEvaluator(test, testOn=true, testOff=true)
:= model.node := model.node
:= fuzz.node) := fuzz.node)