riscv/rocket-chip
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simplify amo_mask generation

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Howard Mao
2016-07-07 12:14:45 -07:00
parent 1c5e7be75b
commit 7cc64011fb
1 changed files with 3 additions and 2 deletions
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5
uncore/src/main/scala/tilelink/Definitions.scala
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@@ -183,8 +183,9 @@ trait HasAcquireUnion extends HasTileLinkParameters {
/** Write mask for [[uncore.Put]], [[uncore.PutBlock]], [[uncore.PutAtomic]] */ /** Write mask for [[uncore.Put]], [[uncore.PutBlock]], [[uncore.PutAtomic]] */
def wmask(dummy: Int = 0): UInt = { def wmask(dummy: Int = 0): UInt = {
val is_amo = isBuiltInType(Acquire.putAtomicType) val is_amo = isBuiltInType(Acquire.putAtomicType)
val amo_sel = if (tlByteAddrBits > log2Up(amoAluOperandBytes)) UIntToOH(amo_offset()) else UInt(1) val amo_mask = if (tlByteAddrBits > log2Up(amoAluOperandBytes))
val amo_mask = FillInterleaved(amoAluOperandBytes, amo_sel) FillInterleaved(amoAluOperandBytes, UIntToOH(amo_offset()))
else Acquire.fullWriteMask
val is_put = isBuiltInType(Acquire.putBlockType) || isBuiltInType(Acquire.putType) val is_put = isBuiltInType(Acquire.putBlockType) || isBuiltInType(Acquire.putType)
val put_mask = union(tlWriteMaskBits, 1) val put_mask = union(tlWriteMaskBits, 1)
Mux(is_amo, amo_mask, Mux(is_put, put_mask, UInt(0))) Mux(is_amo, amo_mask, Mux(is_put, put_mask, UInt(0)))