riscv/rocket-chip
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HTIF now controls CPU reset

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This commit is contained in:
Andrew Waterman
2012-02-22 19:30:03 -08:00
parent 3eebf40310
commit 7c929afe2b
3 changed files with 10 additions and 6 deletions
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3
rocket/src/main/scala/cpu.scala
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@ -19,7 +19,7 @@ class ioRocket extends Bundle()
val dmem = new ioDmem().flip();
}
class rocketProc extends Component
class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
{
val io = new ioRocket();
@ -32,7 +32,6 @@ class rocketProc extends Component
val ptw = new rocketPTW();
val arb = new rocketDmemArbiter();
ctrl.io.htif_reset := io.host.reset
ctrl.io.dpath <> dpath.io.ctrl;
dpath.io.host <> io.host;
dpath.io.debug <> io.debug;