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Resurrect the backup memory port

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We need this to work for our chip, and it's not been tested in a long
time in upstream -- it didn't even used to build since the Nasti
conversion.  This makes a few changes:

 * Rather than calling the backup memory port parameters MEM_*, it calls
   them MIF_* (to match the MIT* paramater objects).  A new name was
   necessary because the Nasti stuff is now dumped as MEM_*, which has
   similar names but incompatible values.

 * p(MIFDataBits) was changed back to 128, as otherwise the backup
   memory port doesn't work (it only send half a TileLink transaction).
   64 also causes readmemh to bail out, but changing the elf2hex parameters
   works around that.

 * A configuration was added that enabled the backup memory port in the
   tester.  While this is kind of an awkward way to do it, I want to
   make sure I can start testing this regularly and this makes it easy to
   integrate.
This commit is contained in:
Palmer Dabbelt
2016-02-26 01:29:38 -08:00
parent 68a49c7700
commit 7c0c48fac4
4 changed files with 24 additions and 22 deletions
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14
vsrc/rocketTestHarness.v
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@ -88,12 +88,12 @@ module rocketTestHarness;
end
wire mem_bk_req_valid, mem_bk_req_rw, mem_bk_req_data_valid;
wire [`MEM_ID_BITS-1:0] mem_bk_req_tag;
wire [`MEM_ADDR_BITS-1:0] mem_bk_req_addr;
wire [`MEM_DATA_BITS-1:0] mem_bk_req_data_bits;
wire [`MIF_TAG_BITS-1:0] mem_bk_req_tag;
wire [`MIF_ADDR_BITS-1:0] mem_bk_req_addr;
wire [`MIF_DATA_BITS-1:0] mem_bk_req_data_bits;
wire mem_bk_req_ready, mem_bk_req_data_ready, mem_bk_resp_valid;
wire [`MEM_ID_BITS-1:0] mem_bk_resp_tag;
wire [`MEM_DATA_BITS-1:0] mem_bk_resp_data;
wire [`MIF_TAG_BITS-1:0] mem_bk_resp_tag;
wire [`MIF_DATA_BITS-1:0] mem_bk_resp_data;
`ifdef MEM_BACKUP_EN
memdessertMemDessert dessert
@ -150,9 +150,9 @@ module rocketTestHarness;
assign mem_in_bits = {`HTIF_WIDTH {1'b0}};
assign mem_bk_req_valid = 1'b0;
assign mem_bk_req_ready = 1'b0;
assign mem_bk_req_addr = {`MEM_ADDR_BITS {1'b0}};
assign mem_bk_req_addr = {`MIF_ADDR_BITS {1'b0}};
assign mem_bk_req_rw = 1'b0;
assign mem_bk_req_tag = {`MEM_ID_BITS {1'b0}};
assign mem_bk_req_tag = {`MIF_TAG_BITS {1'b0}};
assign mem_bk_req_data_valid = 1'b0;
assign mem_bk_req_data_bits = 16'd0;
`endif