riscv/rocket-chip
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Don't emit PTW covers when !usingVM

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This commit is contained in:
Andrew Waterman
2017-11-03 15:03:27 -07:00
committed by GitHub
parent 7e75d63ba6
commit 7bef935d2a
1 changed files with 3 additions and 5 deletions
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4
src/main/scala/rocket/PTW.scala
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@@ -279,13 +279,11 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
count := pgLevels-1
}
if (usingVM) {
ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access")
ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table")
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
cover(cond, s"PTW_$label", "MemorySystem;;" + desc)
if (usingVM) cover(cond, s"PTW_$label", "MemorySystem;;" + desc)
}
/** Mix-ins for constructing tiles that might have a PTW */