riscv/rocket-chip
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Define fetchBytes in HasCoreParams, not Frontend

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It is more generally useful.
This commit is contained in:
Andrew Waterman 2017-09-29 12:31:26 -07:00
parent 2786e42d99
commit 7bcf28c585
2 changed files with 1 additions and 1 deletions
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1
src/main/scala/rocket/Frontend.scala
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@ -75,7 +75,6 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
val icache = outer.icache.module val icache = outer.icache.module
require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes) require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes)
val fetchBytes = coreInstBytes * fetchWidth
val tlb = Module(new TLB(true, log2Ceil(fetchBytes), nTLBEntries)) val tlb = Module(new TLB(true, log2Ceil(fetchBytes), nTLBEntries))
val fq = withReset(reset || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 5, flow = true)) } val fq = withReset(reset || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 5, flow = true)) }

1
src/main/scala/tile/Core.scala
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@ -54,6 +54,7 @@ trait HasCoreParameters extends HasTileParameters {
val fetchWidth = coreParams.fetchWidth val fetchWidth = coreParams.fetchWidth
val decodeWidth = coreParams.decodeWidth val decodeWidth = coreParams.decodeWidth
val fetchBytes = coreParams.fetchBytes
val coreInstBits = coreParams.instBits val coreInstBits = coreParams.instBits
val coreInstBytes = coreInstBits/8 val coreInstBytes = coreInstBits/8
val coreDataBits = xLen max fLen val coreDataBits = xLen max fLen