riscv/rocket-chip
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update README

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Yunsup Lee 2013-05-13 11:19:55 -07:00
parent 5b55cc93af
commit 7ba3ab03e2
1 changed files with 6 additions and 9 deletions
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README
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@ -2,12 +2,10 @@ Quick and dirty instructions:
CHECKOUT THE CODE: CHECKOUT THE CODE:
git submodule init git submodule update --init
git submodule update
cd riscv-gcc-isasim cd riscv-tools
git submodule init git submodule update --init
git submodule update
BUILDING THE TOOLCHAIN: BUILDING THE TOOLCHAIN:
@ -15,7 +13,7 @@ BUILDING THE TOOLCHAIN:
To build RISC-V ISA simulator, frontend server, proxy kernel and newlib based GNU toolchain: To build RISC-V ISA simulator, frontend server, proxy kernel and newlib based GNU toolchain:
export RISCV=/path/to/riscv/toolchain/installation export RISCV=/path/to/riscv/toolchain/installation
cd riscv-gcc-isasim cd riscv-tools
./build.sh ./build.sh
To build asm tests and benchmarks (you must have the RISC-V toolchain installed and in your path): To build asm tests and benchmarks (you must have the RISC-V toolchain installed and in your path):
@ -23,7 +21,7 @@ BUILDING THE TOOLCHAIN:
cd riscv-tests/isa/ cd riscv-tests/isa/
make -j make -j
cd riscv-asmtests-bmarks/riscv-bmarks/ cd riscv-tests/benchmarks
make -j make -j
BUILDING THE PROJECT: BUILDING THE PROJECT:
@ -62,8 +60,7 @@ UPDATING TO A NEWER VERSION OF CHISEL:
To grab a newer version of chisel: To grab a newer version of chisel:
git submodule init git submodule update --init
git submodule update
cd chisel cd chisel
git pull origin master git pull origin master