riscv/rocket-chip
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Don't enter D$ flush state machine if grant outstanding

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This commit is contained in:
Andrew Waterman 2016-10-03 19:55:56 -07:00
parent 28beb33943
commit 7b69f1f261
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/dcache.scala
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@ -474,7 +474,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
when (s2_valid_masked && s2_req.cmd === M_FLUSH_ALL) { when (s2_valid_masked && s2_req.cmd === M_FLUSH_ALL) {
io.cpu.s2_nack := !flushed io.cpu.s2_nack := !flushed
when (!flushed) { when (!flushed) {
flushing := !release_ack_wait flushing := !release_ack_wait && !uncachedInFlight.asUInt.orR
} }
} }
s1_flush_valid := metaReadArb.io.in(0).fire() && !s1_flush_valid && !s2_flush_valid && release_state === s_ready && !release_ack_wait s1_flush_valid := metaReadArb.io.in(0).fire() && !s1_flush_valid && !s2_flush_valid && release_state === s_ready && !release_ack_wait