riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Correctly hook up the Local Interrupts into the Coreplex. Name some IntXBars

Browse Source
This commit is contained in:
Megan Wachs 2017-10-11 13:14:25 -07:00
parent b566ffedea
commit 7b4c48d005
2 changed files with 9 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/main/scala/coreplex/BaseCoreplex.scala
View File

@ -40,8 +40,12 @@ trait HasTiles extends HasSystemBus {
// Handle interrupts to be routed directly into each tile // Handle interrupts to be routed directly into each tile
// TODO: figure out how to merge the localIntNodes and coreIntXbar // TODO: figure out how to merge the localIntNodes and coreIntXbar
def localIntCounts = tileParams.map(_.core.nLocalInterrupts) def localIntCounts = tileParams.map(_.core.nLocalInterrupts)
def localIntNodes = tileParams map { t => lazy val localIntNodes = tileParams.zipWithIndex map { case (t, i) => {
(t.core.nLocalInterrupts > 0).option(LazyModule(new IntXbar).intnode) (t.core.nLocalInterrupts > 0).option({
val n = LazyModule(new IntXbar)
n.suggestName(s"localIntXbar_${i}")
n.intnode})
}
} }
val tiles: Seq[BaseTile] val tiles: Seq[BaseTile]

3
src/main/scala/coreplex/RocketCoreplex.scala
View File

@ -62,16 +62,19 @@ trait HasRocketTiles extends HasTiles
// so may or may not need to be synchronized depending on the Tile's crossing type. // so may or may not need to be synchronized depending on the Tile's crossing type.
// Debug interrupt is definitely asynchronous in all cases. // Debug interrupt is definitely asynchronous in all cases.
val asyncIntXbar = LazyModule(new IntXbar) val asyncIntXbar = LazyModule(new IntXbar)
asyncIntXbar.suggestName("asyncIntXbar")
asyncIntXbar.intnode := debug.intnode // debug asyncIntXbar.intnode := debug.intnode // debug
wrapper.asyncIntNode := asyncIntXbar.intnode wrapper.asyncIntNode := asyncIntXbar.intnode
val periphIntXbar = LazyModule(new IntXbar) val periphIntXbar = LazyModule(new IntXbar)
periphIntXbar.suggestName("periphIntXbar")
periphIntXbar.intnode := clint.intnode // msip+mtip periphIntXbar.intnode := clint.intnode // msip+mtip
periphIntXbar.intnode := plic.intnode // meip periphIntXbar.intnode := plic.intnode // meip
if (tp.core.useVM) periphIntXbar.intnode := plic.intnode // seip if (tp.core.useVM) periphIntXbar.intnode := plic.intnode // seip
wrapper.periphIntNode := periphIntXbar.intnode wrapper.periphIntNode := periphIntXbar.intnode
val coreIntXbar = LazyModule(new IntXbar) val coreIntXbar = LazyModule(new IntXbar)
coreIntXbar.suggestName("coreIntXbar")
lip.foreach { coreIntXbar.intnode := _ } // lip lip.foreach { coreIntXbar.intnode := _ } // lip
wrapper.coreIntNode := coreIntXbar.intnode wrapper.coreIntNode := coreIntXbar.intnode