riscv/rocket-chip
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Correctly hook up the Local Interrupts into the Coreplex. Name some IntXBars

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Megan Wachs
2017-10-11 13:14:25 -07:00
parent b566ffedea
commit 7b4c48d005
2 changed files with 9 additions and 2 deletions
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3
src/main/scala/coreplex/RocketCoreplex.scala
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@ -62,16 +62,19 @@ trait HasRocketTiles extends HasTiles
// so may or may not need to be synchronized depending on the Tile's crossing type.
// Debug interrupt is definitely asynchronous in all cases.
val asyncIntXbar = LazyModule(new IntXbar)
asyncIntXbar.suggestName("asyncIntXbar")
asyncIntXbar.intnode := debug.intnode // debug
wrapper.asyncIntNode := asyncIntXbar.intnode
val periphIntXbar = LazyModule(new IntXbar)
periphIntXbar.suggestName("periphIntXbar")
periphIntXbar.intnode := clint.intnode // msip+mtip
periphIntXbar.intnode := plic.intnode // meip
if (tp.core.useVM) periphIntXbar.intnode := plic.intnode // seip
wrapper.periphIntNode := periphIntXbar.intnode
val coreIntXbar = LazyModule(new IntXbar)
coreIntXbar.suggestName("coreIntXbar")
lip.foreach { coreIntXbar.intnode := _ } // lip
wrapper.coreIntNode := coreIntXbar.intnode