reorganize moving non-submodule packages into src/main/scala
This commit is contained in:
Howard Mao
105
src/main/scala/uncore/util/AmoAlu.scala
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105
src/main/scala/uncore/util/AmoAlu.scala
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// See LICENSE for license details.
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package uncore.util
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import Chisel._
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import uncore.tilelink._
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import cde.Parameters
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import uncore.constants._
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class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) {
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val size = typ(log2Up(log2Up(maxSize)+1)-1,0)
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def misaligned =
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(addr & ((UInt(1) << size) - UInt(1))(log2Up(maxSize)-1,0)).orR
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def mask = {
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var res = UInt(1)
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for (i <- 0 until log2Up(maxSize)) {
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val upper = Mux(addr(i), res, UInt(0)) | Mux(size >= UInt(i+1), UInt((BigInt(1) << (1 << i))-1), UInt(0))
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val lower = Mux(addr(i), UInt(0), res)
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res = Cat(upper, lower)
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}
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res
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}
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protected def genData(i: Int): UInt =
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if (i >= log2Up(maxSize)) dat
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else Mux(size === UInt(i), Fill(1 << (log2Up(maxSize)-i), dat((8 << i)-1,0)), genData(i+1))
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def data = genData(0)
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def wordData = genData(2)
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}
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class StoreGenAligned(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) extends StoreGen(typ, addr, dat, maxSize) {
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override def genData(i: Int) = dat
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}
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class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) {
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private val size = new StoreGen(typ, addr, dat, maxSize).size
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private def genData(logMinSize: Int): UInt = {
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var res = dat
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for (i <- log2Up(maxSize)-1 to logMinSize by -1) {
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val pos = 8 << i
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val shifted = Mux(addr(i), res(2*pos-1,pos), res(pos-1,0))
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val doZero = Bool(i == 0) && zero
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val zeroed = Mux(doZero, UInt(0), shifted)
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res = Cat(Mux(size === UInt(i) || doZero, Fill(8*maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed)
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}
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res
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}
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def wordData = genData(2)
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def data = genData(0)
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}
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class AMOALU(operandBits: Int, rhsIsAligned: Boolean = false)(implicit p: Parameters) extends Module {
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require(operandBits == 32 || operandBits == 64)
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val io = new Bundle {
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val addr = Bits(INPUT, log2Ceil(operandBits/8))
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val cmd = Bits(INPUT, M_SZ)
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val typ = Bits(INPUT, log2Ceil(log2Ceil(operandBits/8) + 1))
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val lhs = Bits(INPUT, operandBits)
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val rhs = Bits(INPUT, operandBits)
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val out = Bits(OUTPUT, operandBits)
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}
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val storegen =
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if(rhsIsAligned) new StoreGenAligned(io.typ, io.addr, io.rhs, operandBits/8)
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else new StoreGen(io.typ, io.addr, io.rhs, operandBits/8)
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val rhs = storegen.wordData
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val sgned = io.cmd === M_XA_MIN || io.cmd === M_XA_MAX
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val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU
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val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU
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val adder_out =
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if (operandBits == 32) io.lhs + rhs
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else {
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val mask = ~UInt(0,64) ^ (io.addr(2) << 31)
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(io.lhs & mask) + (rhs & mask)
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}
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val less =
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if (operandBits == 32) Mux(io.lhs(31) === rhs(31), io.lhs < rhs, Mux(sgned, io.lhs(31), io.rhs(31)))
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else {
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val word = !io.typ(0)
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val cmp_lhs = Mux(word && !io.addr(2), io.lhs(31), io.lhs(63))
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val cmp_rhs = Mux(word && !io.addr(2), rhs(31), rhs(63))
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val lt_lo = io.lhs(31,0) < rhs(31,0)
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val lt_hi = io.lhs(63,32) < rhs(63,32)
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val eq_hi = io.lhs(63,32) === rhs(63,32)
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val lt = Mux(word, Mux(io.addr(2), lt_hi, lt_lo), lt_hi || eq_hi && lt_lo)
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Mux(cmp_lhs === cmp_rhs, lt, Mux(sgned, cmp_lhs, cmp_rhs))
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}
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val out = Mux(io.cmd === M_XA_ADD, adder_out,
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Mux(io.cmd === M_XA_AND, io.lhs & rhs,
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Mux(io.cmd === M_XA_OR, io.lhs | rhs,
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Mux(io.cmd === M_XA_XOR, io.lhs ^ rhs,
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Mux(Mux(less, min, max), io.lhs,
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storegen.data)))))
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val wmask = FillInterleaved(8, storegen.mask)
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io.out := wmask & out | ~wmask & io.lhs
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}
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134
src/main/scala/uncore/util/Counters.scala
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134
src/main/scala/uncore/util/Counters.scala
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@ -0,0 +1,134 @@
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package uncore.util
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import Chisel._
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import uncore.tilelink._
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import cde.Parameters
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// Produces 0-width value when counting to 1
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class ZCounter(val n: Int) {
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val value = Reg(init=UInt(0, log2Ceil(n)))
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def inc(): Bool = {
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if (n == 1) Bool(true)
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else {
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val wrap = value === UInt(n-1)
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value := Mux(Bool(!isPow2(n)) && wrap, UInt(0), value + UInt(1))
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wrap
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}
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}
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}
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object ZCounter {
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def apply(n: Int) = new ZCounter(n)
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def apply(cond: Bool, n: Int): (UInt, Bool) = {
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val c = new ZCounter(n)
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var wrap: Bool = null
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when (cond) { wrap = c.inc() }
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(c.value, cond && wrap)
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}
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}
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object TwoWayCounter {
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def apply(up: Bool, down: Bool, max: Int): UInt = {
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val cnt = Reg(init = UInt(0, log2Up(max+1)))
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when (up && !down) { cnt := cnt + UInt(1) }
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when (down && !up) { cnt := cnt - UInt(1) }
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cnt
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}
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}
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class BeatCounterStatus extends Bundle {
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val idx = UInt()
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val done = Bool()
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}
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class TwoWayBeatCounterStatus extends Bundle {
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val pending = Bool()
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val up = new BeatCounterStatus()
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val down = new BeatCounterStatus()
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}
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/** Utility trait containing wiring functions to keep track of how many data beats have
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* been sent or recieved over a particular [[uncore.TileLinkChannel]] or pair of channels.
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*
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* Won't count message types that don't have data.
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* Used in [[uncore.XactTracker]] and [[uncore.FinishUnit]].
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*/
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trait HasDataBeatCounters {
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type HasBeat = TileLinkChannel with HasTileLinkBeatId
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type HasId = TileLinkChannel with HasClientId
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/** Returns the current count on this channel and when a message is done
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* @param inc increment the counter (usually .valid or .fire())
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* @param data the actual channel data
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* @param beat count to return for single-beat messages
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*/
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def connectDataBeatCounter[S <: TileLinkChannel](inc: Bool, data: S, beat: UInt) = {
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val multi = data.hasMultibeatData()
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val (multi_cnt, multi_done) = Counter(inc && multi, data.tlDataBeats)
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val cnt = Mux(multi, multi_cnt, beat)
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val done = Mux(multi, multi_done, inc)
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(cnt, done)
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}
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/** Counter for beats on outgoing [[chisel.DecoupledIO]] */
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def connectOutgoingDataBeatCounter[T <: TileLinkChannel](
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out: DecoupledIO[T],
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beat: UInt = UInt(0)): (UInt, Bool) =
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connectDataBeatCounter(out.fire(), out.bits, beat)
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/** Returns done but not cnt. Use the addr_beat subbundle instead of cnt for beats on
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* incoming channels in case of network reordering.
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*/
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def connectIncomingDataBeatCounter[T <: TileLinkChannel](in: DecoupledIO[T]): Bool =
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connectDataBeatCounter(in.fire(), in.bits, UInt(0))._2
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/** Counter for beats on incoming DecoupledIO[LogicalNetworkIO[]]s returns done */
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def connectIncomingDataBeatCounterWithHeader[T <: TileLinkChannel](in: DecoupledIO[LogicalNetworkIO[T]]): Bool =
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connectDataBeatCounter(in.fire(), in.bits.payload, UInt(0))._2
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/** If the network might interleave beats from different messages, we need a Vec of counters,
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* one for every outstanding message id that might be interleaved.
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*
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* @param getId mapping from Message to counter id
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*/
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def connectIncomingDataBeatCountersWithHeader[T <: TileLinkChannel with HasClientTransactionId](
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in: DecoupledIO[LogicalNetworkIO[T]],
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entries: Int,
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getId: LogicalNetworkIO[T] => UInt): Vec[Bool] = {
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Vec((0 until entries).map { i =>
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connectDataBeatCounter(in.fire() && getId(in.bits) === UInt(i), in.bits.payload, UInt(0))._2
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})
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}
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/** Provides counters on two channels, as well a meta-counter that tracks how many
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* messages have been sent over the up channel but not yet responded to over the down channel
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*
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* @param status bundle of status of the counters
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* @param up outgoing channel
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* @param down incoming channel
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* @param max max number of outstanding ups with no down
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* @param beat overrides cnts on single-beat messages
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* @param track whether up's message should be tracked
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* @return a tuple containing whether their are outstanding messages, up's count,
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* up's done, down's count, down's done
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*/
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def connectTwoWayBeatCounters[T <: TileLinkChannel, S <: TileLinkChannel](
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status: TwoWayBeatCounterStatus,
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up: DecoupledIO[T],
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down: DecoupledIO[S],
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max: Int = 1,
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beat: UInt = UInt(0),
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trackUp: T => Bool = (t: T) => Bool(true),
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trackDown: S => Bool = (s: S) => Bool(true)) {
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val (up_idx, up_done) = connectDataBeatCounter(up.fire() && trackUp(up.bits), up.bits, beat)
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val (dn_idx, dn_done) = connectDataBeatCounter(down.fire() && trackDown(down.bits), down.bits, beat)
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val cnt = TwoWayCounter(up_done, dn_done, max)
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status.pending := cnt > UInt(0)
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status.up.idx := up_idx
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status.up.done := up_done
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status.down.idx := dn_idx
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status.down.done := dn_done
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}
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}
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56
src/main/scala/uncore/util/Enqueuer.scala
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56
src/main/scala/uncore/util/Enqueuer.scala
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@ -0,0 +1,56 @@
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package uncore.util
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import Chisel._
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import uncore.tilelink._
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import cde.Parameters
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/** Struct for describing per-channel queue depths */
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case class TileLinkDepths(acq: Int, prb: Int, rel: Int, gnt: Int, fin: Int)
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/** Optionally enqueues each [[uncore.TileLinkChannel]] individually */
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class TileLinkEnqueuer(depths: TileLinkDepths)(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val client = new TileLinkIO().flip
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val manager = new TileLinkIO
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}
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io.manager.acquire <> (if(depths.acq > 0) Queue(io.client.acquire, depths.acq) else io.client.acquire)
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io.client.probe <> (if(depths.prb > 0) Queue(io.manager.probe, depths.prb) else io.manager.probe)
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io.manager.release <> (if(depths.rel > 0) Queue(io.client.release, depths.rel) else io.client.release)
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io.client.grant <> (if(depths.gnt > 0) Queue(io.manager.grant, depths.gnt) else io.manager.grant)
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io.manager.finish <> (if(depths.fin > 0) Queue(io.client.finish, depths.fin) else io.client.finish)
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}
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object TileLinkEnqueuer {
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def apply(in: TileLinkIO, depths: TileLinkDepths)(implicit p: Parameters): TileLinkIO = {
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val t = Module(new TileLinkEnqueuer(depths))
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t.io.client <> in
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t.io.manager
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}
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def apply(in: TileLinkIO, depth: Int)(implicit p: Parameters): TileLinkIO = {
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apply(in, TileLinkDepths(depth, depth, depth, depth, depth))
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}
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}
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class ClientTileLinkEnqueuer(depths: TileLinkDepths)(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val inner = new ClientTileLinkIO().flip
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val outer = new ClientTileLinkIO
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}
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io.outer.acquire <> (if(depths.acq > 0) Queue(io.inner.acquire, depths.acq) else io.inner.acquire)
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io.inner.probe <> (if(depths.prb > 0) Queue(io.outer.probe, depths.prb) else io.outer.probe)
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io.outer.release <> (if(depths.rel > 0) Queue(io.inner.release, depths.rel) else io.inner.release)
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io.inner.grant <> (if(depths.gnt > 0) Queue(io.outer.grant, depths.gnt) else io.outer.grant)
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io.outer.finish <> (if(depths.fin > 0) Queue(io.inner.finish, depths.fin) else io.inner.finish)
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}
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object ClientTileLinkEnqueuer {
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def apply(in: ClientTileLinkIO, depths: TileLinkDepths)(implicit p: Parameters): ClientTileLinkIO = {
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val t = Module(new ClientTileLinkEnqueuer(depths))
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t.io.inner <> in
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t.io.outer
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}
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def apply(in: ClientTileLinkIO, depth: Int)(implicit p: Parameters): ClientTileLinkIO = {
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apply(in, TileLinkDepths(depth, depth, depth, depth, depth))
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}
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}
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25
src/main/scala/uncore/util/Package.scala
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25
src/main/scala/uncore/util/Package.scala
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@ -0,0 +1,25 @@
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package uncore
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import Chisel._
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package object util {
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implicit class UIntIsOneOf(val x: UInt) extends AnyVal {
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def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).reduce(_||_)
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def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
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}
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implicit class SeqToAugmentedSeq[T <: Data](val x: Seq[T]) extends AnyVal {
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def apply(idx: UInt): T = {
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if (x.size == 1) {
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x.head
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} else {
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val half = 1 << (log2Ceil(x.size) - 1)
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val newIdx = idx & UInt(half - 1)
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Mux(idx >= UInt(half), x.drop(half)(newIdx), x.take(half)(newIdx))
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}
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}
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def asUInt(): UInt = Cat(x.map(_.asUInt).reverse)
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}
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}
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69
src/main/scala/uncore/util/Serializer.scala
Normal file
69
src/main/scala/uncore/util/Serializer.scala
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@ -0,0 +1,69 @@
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// See LICENSE for license details.
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package uncore.util
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import Chisel._
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import uncore.tilelink._
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class FlowThroughSerializer[T <: Bundle with HasTileLinkData](gen: T, n: Int) extends Module {
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val io = new Bundle {
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val in = Decoupled(gen).flip
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val out = Decoupled(gen)
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val cnt = UInt(OUTPUT, log2Up(n))
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val done = Bool(OUTPUT)
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}
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val narrowWidth = io.in.bits.data.getWidth / n
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require(io.in.bits.data.getWidth % narrowWidth == 0)
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if(n == 1) {
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io.out <> io.in
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io.cnt := UInt(0)
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io.done := Bool(true)
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} else {
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val cnt = Reg(init=UInt(0, width = log2Up(n)))
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val wrap = cnt === UInt(n-1)
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val rbits = Reg{io.in.bits}
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val active = Reg(init=Bool(false))
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val shifter = Wire(Vec(n, Bits(width = narrowWidth)))
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(0 until n).foreach {
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i => shifter(i) := rbits.data((i+1)*narrowWidth-1,i*narrowWidth)
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}
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io.done := Bool(false)
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io.cnt := cnt
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io.in.ready := !active
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io.out.valid := active || io.in.valid
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io.out.bits := io.in.bits
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when(!active && io.in.valid) {
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when(io.in.bits.hasData()) {
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cnt := Mux(io.out.ready, UInt(1), UInt(0))
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rbits := io.in.bits
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active := Bool(true)
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}
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io.done := !io.in.bits.hasData()
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}
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when(active) {
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io.out.bits := rbits
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io.out.bits.data := shifter(cnt)
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when(io.out.ready) {
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cnt := cnt + UInt(1)
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when(wrap) {
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cnt := UInt(0)
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io.done := Bool(true)
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active := Bool(false)
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}
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}
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}
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}
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}
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object FlowThroughSerializer {
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def apply[T <: Bundle with HasTileLinkData](in: DecoupledIO[T], n: Int): DecoupledIO[T] = {
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val fs = Module(new FlowThroughSerializer(in.bits, n))
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fs.io.in.valid := in.valid
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fs.io.in.bits := in.bits
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in.ready := fs.io.in.ready
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fs.io.out
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}
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}
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