reorganize moving non-submodule packages into src/main/scala
This commit is contained in:
Howard Mao
589
src/main/scala/rocket/csr.scala
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589
src/main/scala/rocket/csr.scala
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@ -0,0 +1,589 @@
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// See LICENSE for license details.
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package rocket
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import Chisel._
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import Util._
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import Instructions._
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import cde.{Parameters, Field}
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import uncore.devices._
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import uncore.util._
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import junctions.AddrMap
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class MStatus extends Bundle {
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val debug = Bool() // not truly part of mstatus, but convenient
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val prv = UInt(width = PRV.SZ) // not truly part of mstatus, but convenient
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val sd = Bool()
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val zero3 = UInt(width = 31)
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val sd_rv32 = Bool()
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val zero2 = UInt(width = 2)
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val vm = UInt(width = 5)
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val zero1 = UInt(width = 4)
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val mxr = Bool()
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val pum = Bool()
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val mprv = Bool()
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val xs = UInt(width = 2)
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val fs = UInt(width = 2)
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val mpp = UInt(width = 2)
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val hpp = UInt(width = 2)
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val spp = UInt(width = 1)
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val mpie = Bool()
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val hpie = Bool()
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val spie = Bool()
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val upie = Bool()
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val mie = Bool()
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val hie = Bool()
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val sie = Bool()
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val uie = Bool()
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}
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class DCSR extends Bundle {
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val xdebugver = UInt(width = 2)
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val ndreset = Bool()
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val fullreset = Bool()
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val hwbpcount = UInt(width = 12)
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val ebreakm = Bool()
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val ebreakh = Bool()
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val ebreaks = Bool()
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val ebreaku = Bool()
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val zero2 = Bool()
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val stopcycle = Bool()
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val stoptime = Bool()
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val cause = UInt(width = 3)
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val debugint = Bool()
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val zero1 = Bool()
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val halt = Bool()
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val step = Bool()
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val prv = UInt(width = PRV.SZ)
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}
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class MIP extends Bundle {
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val rocc = Bool()
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val meip = Bool()
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val heip = Bool()
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val seip = Bool()
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val ueip = Bool()
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val mtip = Bool()
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val htip = Bool()
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val stip = Bool()
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val utip = Bool()
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val msip = Bool()
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val hsip = Bool()
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val ssip = Bool()
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val usip = Bool()
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}
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class PTBR(implicit p: Parameters) extends CoreBundle()(p) {
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require(maxPAddrBits - pgIdxBits + asIdBits <= xLen)
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val asid = UInt(width = asIdBits)
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val ppn = UInt(width = maxPAddrBits - pgIdxBits)
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}
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object PRV
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{
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val SZ = 2
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val U = 0
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val S = 1
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val H = 2
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val M = 3
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}
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object CSR
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{
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// commands
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val SZ = 3
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val X = BitPat.dontCare(SZ)
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val N = UInt(0,SZ)
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val W = UInt(1,SZ)
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val S = UInt(2,SZ)
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val C = UInt(3,SZ)
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val I = UInt(4,SZ)
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val R = UInt(5,SZ)
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val ADDRSZ = 12
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}
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class CSRFileIO(implicit p: Parameters) extends CoreBundle {
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val prci = new PRCITileIO().flip
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val rw = new Bundle {
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val addr = UInt(INPUT, CSR.ADDRSZ)
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val cmd = Bits(INPUT, CSR.SZ)
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val rdata = Bits(OUTPUT, xLen)
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val wdata = Bits(INPUT, xLen)
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}
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val csr_stall = Bool(OUTPUT)
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val csr_xcpt = Bool(OUTPUT)
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val eret = Bool(OUTPUT)
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val singleStep = Bool(OUTPUT)
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val status = new MStatus().asOutput
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val ptbr = new PTBR().asOutput
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val evec = UInt(OUTPUT, vaddrBitsExtended)
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val exception = Bool(INPUT)
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val retire = UInt(INPUT, log2Up(1+retireWidth))
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val custom_mrw_csrs = Vec(nCustomMrwCsrs, UInt(INPUT, xLen))
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val cause = UInt(INPUT, xLen)
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val pc = UInt(INPUT, vaddrBitsExtended)
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val badaddr = UInt(INPUT, vaddrBitsExtended)
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val fatc = Bool(OUTPUT)
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val time = UInt(OUTPUT, xLen)
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val fcsr_rm = Bits(OUTPUT, FPConstants.RM_SZ)
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val fcsr_flags = Valid(Bits(width = FPConstants.FLAGS_SZ)).flip
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val rocc = new RoCCInterface().flip
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val interrupt = Bool(OUTPUT)
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val interrupt_cause = UInt(OUTPUT, xLen)
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val bp = Vec(p(NBreakpoints), new BP).asOutput
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}
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class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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{
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val io = new CSRFileIO
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val reset_mstatus = Wire(init=new MStatus().fromBits(0))
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reset_mstatus.mpp := PRV.M
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reset_mstatus.prv := PRV.M
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val reg_mstatus = Reg(init=reset_mstatus)
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val new_prv = Wire(init = reg_mstatus.prv)
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reg_mstatus.prv := legalizePrivilege(new_prv)
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val reset_dcsr = Wire(init=new DCSR().fromBits(0))
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reset_dcsr.xdebugver := 1
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reset_dcsr.prv := PRV.M
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val reg_dcsr = Reg(init=reset_dcsr)
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val (supported_interrupts, delegable_interrupts) = {
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val sup = Wire(init=new MIP().fromBits(0))
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sup.ssip := Bool(p(UseVM))
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sup.msip := true
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sup.stip := Bool(p(UseVM))
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sup.mtip := true
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sup.meip := true
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sup.seip := Bool(p(UseVM))
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sup.rocc := usingRoCC
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val del = Wire(init=sup)
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del.msip := false
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del.mtip := false
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del.meip := false
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(sup.asUInt, del.asUInt)
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}
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val delegable_exceptions = UInt(Seq(
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Causes.misaligned_fetch,
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Causes.fault_fetch,
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Causes.breakpoint,
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Causes.fault_load,
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Causes.fault_store,
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Causes.user_ecall).map(1 << _).sum)
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val exception = io.exception || io.csr_xcpt
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val reg_debug = Reg(init=Bool(false))
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val reg_dpc = Reg(UInt(width = vaddrBitsExtended))
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val reg_dscratch = Reg(UInt(width = xLen))
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val reg_singleStepped = Reg(Bool())
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when (io.retire(0) || exception) { reg_singleStepped := true }
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when (!io.singleStep) { reg_singleStepped := false }
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assert(!io.singleStep || io.retire <= UInt(1))
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assert(!reg_singleStepped || io.retire === UInt(0))
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val reg_tdrselect = Reg(new TDRSelect)
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val reg_bp = Reg(Vec(1 << log2Up(p(NBreakpoints)), new BP))
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val reg_mie = Reg(init=UInt(0, xLen))
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val reg_mideleg = Reg(init=UInt(0, xLen))
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val reg_medeleg = Reg(init=UInt(0, xLen))
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val reg_mip = Reg(new MIP)
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val reg_mepc = Reg(UInt(width = vaddrBitsExtended))
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val reg_mcause = Reg(Bits(width = xLen))
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val reg_mbadaddr = Reg(UInt(width = vaddrBitsExtended))
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val reg_mscratch = Reg(Bits(width = xLen))
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val reg_mtvec = Reg(init=UInt(p(MtvecInit), paddrBits min xLen))
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val reg_sepc = Reg(UInt(width = vaddrBitsExtended))
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val reg_scause = Reg(Bits(width = xLen))
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val reg_sbadaddr = Reg(UInt(width = vaddrBitsExtended))
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val reg_sscratch = Reg(Bits(width = xLen))
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val reg_stvec = Reg(UInt(width = vaddrBits))
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val reg_sptbr = Reg(new PTBR)
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val reg_wfi = Reg(init=Bool(false))
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val reg_fflags = Reg(UInt(width = 5))
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val reg_frm = Reg(UInt(width = 3))
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val reg_instret = WideCounter(64, io.retire)
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val reg_cycle: UInt = if (enableCommitLog) { reg_instret } else { WideCounter(64) }
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val mip = Wire(init=reg_mip)
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mip.rocc := io.rocc.interrupt
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val read_mip = mip.asUInt & supported_interrupts
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val pending_interrupts = read_mip & reg_mie
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val m_interrupts = Mux(!reg_debug && (reg_mstatus.prv < PRV.M || (reg_mstatus.prv === PRV.M && reg_mstatus.mie)), pending_interrupts & ~reg_mideleg, UInt(0))
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val s_interrupts = Mux(!reg_debug && (reg_mstatus.prv < PRV.S || (reg_mstatus.prv === PRV.S && reg_mstatus.sie)), pending_interrupts & reg_mideleg, UInt(0))
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val all_interrupts = m_interrupts | s_interrupts
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val interruptMSB = BigInt(1) << (xLen-1)
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val interruptCause = interruptMSB + PriorityEncoder(all_interrupts)
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io.interrupt := all_interrupts.orR && !io.singleStep || reg_singleStepped
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io.interrupt_cause := interruptCause
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io.bp := reg_bp take p(NBreakpoints)
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val debugIntCause = reg_mip.getWidth
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// debug interrupts are only masked by being in debug mode
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when (Bool(usingDebug) && reg_dcsr.debugint && !reg_debug) {
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io.interrupt := true
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io.interrupt_cause := interruptMSB + debugIntCause
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}
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val system_insn = io.rw.cmd === CSR.I
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val cpu_ren = io.rw.cmd =/= CSR.N && !system_insn
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val isa_string = "IM" +
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(if (usingVM) "S" else "") +
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(if (usingUser) "U" else "") +
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(if (usingAtomics) "A" else "") +
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(if (usingFPU) "FD" else "") +
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(if (usingRoCC) "X" else "")
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val isa = (BigInt(log2Ceil(xLen) - 4) << (xLen-2)) |
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isa_string.map(x => 1 << (x - 'A')).reduce(_|_)
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val read_mstatus = io.status.asUInt()(xLen-1,0)
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val read_mapping = collection.mutable.LinkedHashMap[Int,Bits](
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CSRs.tdrselect -> reg_tdrselect.asUInt,
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CSRs.tdrdata1 -> reg_bp(reg_tdrselect.tdrindex).control.asUInt,
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CSRs.tdrdata2 -> reg_bp(reg_tdrselect.tdrindex).address,
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CSRs.mimpid -> UInt(0),
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CSRs.marchid -> UInt(0),
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CSRs.mvendorid -> UInt(0),
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CSRs.mcycle -> reg_cycle,
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CSRs.minstret -> reg_instret,
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CSRs.mucounteren -> UInt(0),
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CSRs.mutime_delta -> UInt(0),
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CSRs.mucycle_delta -> UInt(0),
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CSRs.muinstret_delta -> UInt(0),
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CSRs.misa -> UInt(isa),
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CSRs.mstatus -> read_mstatus,
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CSRs.mtvec -> reg_mtvec,
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CSRs.mip -> read_mip,
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CSRs.mie -> reg_mie,
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CSRs.mideleg -> reg_mideleg,
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CSRs.medeleg -> reg_medeleg,
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CSRs.mscratch -> reg_mscratch,
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CSRs.mepc -> reg_mepc.sextTo(xLen),
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CSRs.mbadaddr -> reg_mbadaddr.sextTo(xLen),
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CSRs.mcause -> reg_mcause,
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CSRs.mhartid -> io.prci.id)
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if (usingDebug) {
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read_mapping += CSRs.dcsr -> reg_dcsr.asUInt
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read_mapping += CSRs.dpc -> reg_dpc.asUInt
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read_mapping += CSRs.dscratch -> reg_dscratch.asUInt
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}
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if (usingFPU) {
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read_mapping += CSRs.fflags -> reg_fflags
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read_mapping += CSRs.frm -> reg_frm
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read_mapping += CSRs.fcsr -> Cat(reg_frm, reg_fflags)
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}
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if (usingVM) {
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val read_sie = reg_mie & reg_mideleg
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val read_sip = read_mip & reg_mideleg
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val read_sstatus = Wire(init=io.status)
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read_sstatus.vm := 0
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read_sstatus.mprv := 0
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read_sstatus.mpp := 0
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read_sstatus.hpp := 0
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read_sstatus.mpie := 0
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read_sstatus.hpie := 0
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read_sstatus.mie := 0
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read_sstatus.hie := 0
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read_mapping += CSRs.sstatus -> (read_sstatus.asUInt())(xLen-1,0)
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read_mapping += CSRs.sip -> read_sip.asUInt
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read_mapping += CSRs.sie -> read_sie.asUInt
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read_mapping += CSRs.sscratch -> reg_sscratch
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read_mapping += CSRs.scause -> reg_scause
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read_mapping += CSRs.sbadaddr -> reg_sbadaddr.sextTo(xLen)
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read_mapping += CSRs.sptbr -> reg_sptbr.asUInt
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read_mapping += CSRs.sepc -> reg_sepc.sextTo(xLen)
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read_mapping += CSRs.stvec -> reg_stvec.sextTo(xLen)
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read_mapping += CSRs.mscounteren -> UInt(0)
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read_mapping += CSRs.mstime_delta -> UInt(0)
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read_mapping += CSRs.mscycle_delta -> UInt(0)
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read_mapping += CSRs.msinstret_delta -> UInt(0)
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}
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if (xLen == 32) {
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read_mapping += CSRs.mcycleh -> (reg_cycle >> 32)
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read_mapping += CSRs.minstreth -> (reg_instret >> 32)
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read_mapping += CSRs.mutime_deltah -> UInt(0)
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read_mapping += CSRs.mucycle_deltah -> UInt(0)
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read_mapping += CSRs.muinstret_deltah -> UInt(0)
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if (usingVM) {
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read_mapping += CSRs.mstime_deltah -> UInt(0)
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read_mapping += CSRs.mscycle_deltah -> UInt(0)
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read_mapping += CSRs.msinstret_deltah -> UInt(0)
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}
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}
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for (i <- 0 until nCustomMrwCsrs) {
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val addr = 0xff0 + i
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require(addr < (1 << CSR.ADDRSZ))
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require(!read_mapping.contains(addr), "custom MRW CSR address " + i + " is already in use")
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read_mapping += addr -> io.custom_mrw_csrs(i)
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}
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val decoded_addr = read_mapping map { case (k, v) => k -> (io.rw.addr === k) }
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val addr_valid = decoded_addr.values.reduce(_||_)
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val fp_csr =
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if (usingFPU) decoded_addr(CSRs.fflags) || decoded_addr(CSRs.frm) || decoded_addr(CSRs.fcsr)
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else Bool(false)
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val csr_debug = Bool(usingDebug) && io.rw.addr(5)
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val csr_addr_priv = Cat(io.rw.addr(6,5).andR, io.rw.addr(9,8))
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val priv_sufficient = Cat(reg_debug, reg_mstatus.prv) >= csr_addr_priv
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val read_only = io.rw.addr(11,10).andR
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val cpu_wen = cpu_ren && io.rw.cmd =/= CSR.R && priv_sufficient
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val wen = cpu_wen && !read_only
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val wdata = (Mux(io.rw.cmd.isOneOf(CSR.S, CSR.C), io.rw.rdata, UInt(0)) |
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Mux(io.rw.cmd =/= CSR.C, io.rw.wdata, UInt(0))) &
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~Mux(io.rw.cmd === CSR.C, io.rw.wdata, UInt(0))
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val do_system_insn = priv_sufficient && system_insn
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val opcode = UInt(1) << io.rw.addr(2,0)
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val insn_call = do_system_insn && opcode(0)
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val insn_break = do_system_insn && opcode(1)
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val insn_ret = do_system_insn && opcode(2)
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val insn_sfence_vm = do_system_insn && opcode(4)
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val insn_wfi = do_system_insn && opcode(5)
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io.csr_xcpt := (cpu_wen && read_only) ||
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(cpu_ren && (!priv_sufficient || !addr_valid || fp_csr && !io.status.fs.orR)) ||
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(system_insn && !priv_sufficient) ||
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insn_call || insn_break
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when (insn_wfi) { reg_wfi := true }
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when (pending_interrupts.orR) { reg_wfi := false }
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val cause =
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Mux(!io.csr_xcpt, io.cause,
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Mux(insn_call, reg_mstatus.prv + Causes.user_ecall,
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Mux[UInt](insn_break, Causes.breakpoint, Causes.illegal_instruction)))
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val cause_lsbs = cause(log2Up(xLen)-1,0)
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val causeIsDebugInt = cause(xLen-1) && cause_lsbs === debugIntCause
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val causeIsDebugBreak = cause === Causes.breakpoint && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv)
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val trapToDebug = Bool(usingDebug) && (reg_singleStepped || causeIsDebugInt || causeIsDebugBreak || reg_debug)
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val delegate = Bool(p(UseVM)) && reg_mstatus.prv < PRV.M && Mux(cause(xLen-1), reg_mideleg(cause_lsbs), reg_medeleg(cause_lsbs))
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val debugTVec = Mux(reg_debug, UInt(0x808), UInt(0x800))
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val tvec = Mux(trapToDebug, debugTVec, Mux(delegate, reg_stvec.sextTo(vaddrBitsExtended), reg_mtvec))
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val epc = Mux(csr_debug, reg_dpc, Mux(Bool(p(UseVM)) && !csr_addr_priv(1), reg_sepc, reg_mepc))
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io.fatc := insn_sfence_vm
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io.evec := Mux(exception, tvec, epc)
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io.ptbr := reg_sptbr
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io.eret := insn_ret
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io.singleStep := reg_dcsr.step && !reg_debug
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io.status := reg_mstatus
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io.status.sd := io.status.fs.andR || io.status.xs.andR
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io.status.debug := reg_debug
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if (xLen == 32)
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io.status.sd_rv32 := io.status.sd
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when (exception) {
|
||||
val epc = ~(~io.pc | (coreInstBytes-1))
|
||||
val pie = read_mstatus(reg_mstatus.prv)
|
||||
|
||||
val write_badaddr = cause isOneOf (Causes.breakpoint,
|
||||
Causes.misaligned_load, Causes.misaligned_store, Causes.misaligned_fetch,
|
||||
Causes.fault_load, Causes.fault_store, Causes.fault_fetch)
|
||||
|
||||
when (trapToDebug) {
|
||||
reg_debug := true
|
||||
reg_dpc := epc
|
||||
reg_dcsr.cause := Mux(reg_singleStepped, UInt(4), Mux(causeIsDebugInt, UInt(3), UInt(1)))
|
||||
reg_dcsr.prv := trimPrivilege(reg_mstatus.prv)
|
||||
}.elsewhen (delegate) {
|
||||
reg_sepc := epc
|
||||
reg_scause := cause
|
||||
when (write_badaddr) { reg_sbadaddr := io.badaddr }
|
||||
reg_mstatus.spie := pie
|
||||
reg_mstatus.spp := reg_mstatus.prv
|
||||
reg_mstatus.sie := false
|
||||
new_prv := PRV.S
|
||||
}.otherwise {
|
||||
reg_mepc := epc
|
||||
reg_mcause := cause
|
||||
when (write_badaddr) { reg_mbadaddr := io.badaddr }
|
||||
reg_mstatus.mpie := pie
|
||||
reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv)
|
||||
reg_mstatus.mie := false
|
||||
new_prv := PRV.M
|
||||
}
|
||||
}
|
||||
|
||||
when (insn_ret) {
|
||||
when (Bool(p(UseVM)) && !csr_addr_priv(1)) {
|
||||
when (reg_mstatus.spp.toBool) { reg_mstatus.sie := reg_mstatus.spie }
|
||||
reg_mstatus.spie := false
|
||||
reg_mstatus.spp := PRV.U
|
||||
new_prv := reg_mstatus.spp
|
||||
}.elsewhen (csr_debug) {
|
||||
new_prv := reg_dcsr.prv
|
||||
reg_debug := false
|
||||
}.otherwise {
|
||||
when (reg_mstatus.mpp(1)) { reg_mstatus.mie := reg_mstatus.mpie }
|
||||
.elsewhen (Bool(usingVM) && reg_mstatus.mpp(0)) { reg_mstatus.sie := reg_mstatus.mpie }
|
||||
reg_mstatus.mpie := false
|
||||
reg_mstatus.mpp := legalizePrivilege(PRV.U)
|
||||
new_prv := reg_mstatus.mpp
|
||||
}
|
||||
}
|
||||
|
||||
assert(PopCount(insn_ret :: io.exception :: io.csr_xcpt :: Nil) <= 1, "these conditions must be mutually exclusive")
|
||||
|
||||
io.time := reg_cycle
|
||||
io.csr_stall := reg_wfi
|
||||
|
||||
io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v)
|
||||
|
||||
io.fcsr_rm := reg_frm
|
||||
when (io.fcsr_flags.valid) {
|
||||
reg_fflags := reg_fflags | io.fcsr_flags.bits
|
||||
}
|
||||
|
||||
when (wen) {
|
||||
when (decoded_addr(CSRs.mstatus)) {
|
||||
val new_mstatus = new MStatus().fromBits(wdata)
|
||||
reg_mstatus.mie := new_mstatus.mie
|
||||
reg_mstatus.mpie := new_mstatus.mpie
|
||||
|
||||
if (usingUser) {
|
||||
reg_mstatus.mprv := new_mstatus.mprv
|
||||
reg_mstatus.mpp := trimPrivilege(new_mstatus.mpp)
|
||||
if (usingVM) {
|
||||
reg_mstatus.mxr := new_mstatus.mxr
|
||||
reg_mstatus.pum := new_mstatus.pum
|
||||
reg_mstatus.spp := new_mstatus.spp
|
||||
reg_mstatus.spie := new_mstatus.spie
|
||||
reg_mstatus.sie := new_mstatus.sie
|
||||
}
|
||||
}
|
||||
|
||||
if (usingVM) {
|
||||
require(if (xLen == 32) pgLevels == 2 else pgLevels > 2 && pgLevels < 6)
|
||||
val vm_on = 6 + pgLevels // TODO Sv48 support should imply Sv39 support
|
||||
when (new_mstatus.vm === 0) { reg_mstatus.vm := 0 }
|
||||
when (new_mstatus.vm === vm_on) { reg_mstatus.vm := vm_on }
|
||||
}
|
||||
if (usingVM || usingFPU) reg_mstatus.fs := Fill(2, new_mstatus.fs.orR)
|
||||
if (usingRoCC) reg_mstatus.xs := Fill(2, new_mstatus.xs.orR)
|
||||
}
|
||||
when (decoded_addr(CSRs.mip)) {
|
||||
val new_mip = new MIP().fromBits(wdata)
|
||||
if (usingVM) {
|
||||
reg_mip.ssip := new_mip.ssip
|
||||
reg_mip.stip := new_mip.stip
|
||||
}
|
||||
}
|
||||
when (decoded_addr(CSRs.mie)) { reg_mie := wdata & supported_interrupts }
|
||||
when (decoded_addr(CSRs.mepc)) { reg_mepc := ~(~wdata | (coreInstBytes-1)) }
|
||||
when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata }
|
||||
if (p(MtvecWritable))
|
||||
when (decoded_addr(CSRs.mtvec)) { reg_mtvec := wdata >> 2 << 2 }
|
||||
when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & UInt((BigInt(1) << (xLen-1)) + 31) /* only implement 5 LSBs and MSB */ }
|
||||
when (decoded_addr(CSRs.mbadaddr)) { reg_mbadaddr := wdata(vaddrBitsExtended-1,0) }
|
||||
if (usingFPU) {
|
||||
when (decoded_addr(CSRs.fflags)) { reg_fflags := wdata }
|
||||
when (decoded_addr(CSRs.frm)) { reg_frm := wdata }
|
||||
when (decoded_addr(CSRs.fcsr)) { reg_fflags := wdata; reg_frm := wdata >> reg_fflags.getWidth }
|
||||
}
|
||||
if (usingDebug) {
|
||||
when (decoded_addr(CSRs.dcsr)) {
|
||||
val new_dcsr = new DCSR().fromBits(wdata)
|
||||
reg_dcsr.halt := new_dcsr.halt
|
||||
reg_dcsr.step := new_dcsr.step
|
||||
reg_dcsr.ebreakm := new_dcsr.ebreakm
|
||||
if (usingVM) reg_dcsr.ebreaks := new_dcsr.ebreaks
|
||||
if (usingUser) reg_dcsr.ebreaku := new_dcsr.ebreaku
|
||||
if (usingUser) reg_dcsr.prv := trimPrivilege(new_dcsr.prv)
|
||||
}
|
||||
when (decoded_addr(CSRs.dpc)) { reg_dpc := ~(~wdata | (coreInstBytes-1)) }
|
||||
when (decoded_addr(CSRs.dscratch)) { reg_dscratch := wdata }
|
||||
}
|
||||
if (usingVM) {
|
||||
when (decoded_addr(CSRs.sstatus)) {
|
||||
val new_sstatus = new MStatus().fromBits(wdata)
|
||||
reg_mstatus.sie := new_sstatus.sie
|
||||
reg_mstatus.spie := new_sstatus.spie
|
||||
reg_mstatus.spp := new_sstatus.spp
|
||||
reg_mstatus.pum := new_sstatus.pum
|
||||
reg_mstatus.fs := Fill(2, new_sstatus.fs.orR) // even without an FPU
|
||||
if (usingRoCC) reg_mstatus.xs := Fill(2, new_sstatus.xs.orR)
|
||||
}
|
||||
when (decoded_addr(CSRs.sip)) {
|
||||
val new_sip = new MIP().fromBits(wdata)
|
||||
reg_mip.ssip := new_sip.ssip
|
||||
}
|
||||
when (decoded_addr(CSRs.sie)) { reg_mie := (reg_mie & ~reg_mideleg) | (wdata & reg_mideleg) }
|
||||
when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata }
|
||||
when (decoded_addr(CSRs.sptbr)) { reg_sptbr.ppn := wdata(ppnBits-1,0) }
|
||||
when (decoded_addr(CSRs.sepc)) { reg_sepc := ~(~wdata | (coreInstBytes-1)) }
|
||||
when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata >> 2 << 2 }
|
||||
when (decoded_addr(CSRs.scause)) { reg_scause := wdata & UInt((BigInt(1) << (xLen-1)) + 31) /* only implement 5 LSBs and MSB */ }
|
||||
when (decoded_addr(CSRs.sbadaddr)) { reg_sbadaddr := wdata(vaddrBitsExtended-1,0) }
|
||||
when (decoded_addr(CSRs.mideleg)) { reg_mideleg := wdata & delegable_interrupts }
|
||||
when (decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata & delegable_exceptions }
|
||||
}
|
||||
if (p(NBreakpoints) > 0) {
|
||||
val newTDR = new TDRSelect().fromBits(wdata)
|
||||
when (decoded_addr(CSRs.tdrselect)) { reg_tdrselect.tdrindex := newTDR.tdrindex }
|
||||
|
||||
when (reg_tdrselect.tdrmode || reg_debug) {
|
||||
when (decoded_addr(CSRs.tdrdata1)) {
|
||||
val newBPC = new BPControl().fromBits(wdata)
|
||||
reg_bp(reg_tdrselect.tdrindex).control := newBPC
|
||||
reg_bp(reg_tdrselect.tdrindex).control.bpmatch := newBPC.bpmatch & 2 /* exact/NAPOT only */
|
||||
}
|
||||
when (decoded_addr(CSRs.tdrdata2)) { reg_bp(reg_tdrselect.tdrindex).address := wdata }
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
reg_mip := io.prci.interrupts
|
||||
reg_dcsr.debugint := io.prci.interrupts.debug
|
||||
reg_dcsr.hwbpcount := UInt(p(NBreakpoints))
|
||||
|
||||
reg_sptbr.asid := 0
|
||||
reg_tdrselect.reserved := 0
|
||||
reg_tdrselect.tdrmode := true // TODO support D-mode breakpoint theft
|
||||
if (reg_bp.isEmpty) reg_tdrselect.tdrindex := 0
|
||||
for (bpc <- reg_bp map {_.control}) {
|
||||
bpc.tdrtype := bpc.tdrType
|
||||
bpc.bpamaskmax := bpc.bpaMaskMax
|
||||
bpc.reserved := 0
|
||||
bpc.bpaction := 0
|
||||
bpc.h := false
|
||||
if (!usingVM) bpc.s := false
|
||||
if (!usingUser) bpc.u := false
|
||||
if (!usingVM && !usingUser) bpc.m := true
|
||||
when (reset) {
|
||||
bpc.r := false
|
||||
bpc.w := false
|
||||
bpc.x := false
|
||||
}
|
||||
}
|
||||
for (bp <- reg_bp drop p(NBreakpoints))
|
||||
bp := new BP().fromBits(0)
|
||||
|
||||
def legalizePrivilege(priv: UInt): UInt =
|
||||
if (usingVM) Mux(priv === PRV.H, PRV.U, priv)
|
||||
else if (usingUser) Fill(2, priv(0))
|
||||
else PRV.M
|
||||
|
||||
def trimPrivilege(priv: UInt): UInt =
|
||||
if (usingVM) priv
|
||||
else legalizePrivilege(priv)
|
||||
}
|
||||
Reference in New Issue
Block a user