reorganize moving non-submodule packages into src/main/scala
This commit is contained in:
Howard Mao
381
src/main/scala/coreplex/Configs.scala
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381
src/main/scala/coreplex/Configs.scala
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// See LICENSE for license details.
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package coreplex
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import Chisel._
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import junctions._
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import uncore.tilelink._
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import uncore.coherence._
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import uncore.agents._
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import uncore.devices._
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import uncore.converters._
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import rocket._
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import rocket.Util._
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import scala.math.max
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import scala.collection.mutable.{LinkedHashSet, ListBuffer}
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import DefaultTestSuites._
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import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
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object ConfigUtils {
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def max_int(values: Int*): Int = {
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values.reduce((a, b) => max(a, b))
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}
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}
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import ConfigUtils._
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class BaseCoreplexConfig extends Config (
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topDefinitions = { (pname,site,here) =>
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type PF = PartialFunction[Any,Any]
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def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
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lazy val innerDataBits = 64
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lazy val innerDataBeats = (8 * site(CacheBlockBytes)) / innerDataBits
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pname match {
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//Memory Parameters
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case PAddrBits => 32
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case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
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case ASIdBits => 7
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//Params used by all caches
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case NSets => findBy(CacheName)
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case NWays => findBy(CacheName)
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case RowBits => findBy(CacheName)
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case NTLBEntries => findBy(CacheName)
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case CacheIdBits => findBy(CacheName)
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case SplitMetadata => findBy(CacheName)
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case "L1I" => {
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case NSets => Knob("L1I_SETS") //64
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case NWays => Knob("L1I_WAYS") //4
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case RowBits => site(TLKey("L1toL2")).dataBitsPerBeat
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case NTLBEntries => 8
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case CacheIdBits => 0
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case SplitMetadata => false
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}:PF
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case "L1D" => {
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case NSets => Knob("L1D_SETS") //64
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case NWays => Knob("L1D_WAYS") //4
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case RowBits => site(TLKey("L1toL2")).dataBitsPerBeat
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case NTLBEntries => 8
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case CacheIdBits => 0
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case SplitMetadata => false
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}:PF
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case ECCCode => None
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case Replacer => () => new RandomReplacement(site(NWays))
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//L1InstCache
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case BtbKey => BtbParameters()
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//L1DataCache
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case DCacheKey => DCacheConfig(nMSHRs = site(Knob("L1D_MSHRS")))
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//L2 Memory System Params
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case AmoAluOperandBits => site(XLen)
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case NAcquireTransactors => 7
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case L2StoreDataQueueDepth => 1
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case L2DirectoryRepresentation => new NullRepresentation(site(NTiles))
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case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
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Module(new L2BroadcastHub()(p.alterPartial({
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMC" })))
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case NCachedTileLinkPorts => 1
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case NUncachedTileLinkPorts => 1
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//Tile Constants
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case BuildTiles => {
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val env = if(site(UseVM)) List("p","v") else List("p")
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site(FPUKey) foreach { case cfg =>
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TestGeneration.addSuite(rv32udBenchmarks)
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TestGeneration.addSuites(env.map(rv64ufNoDiv))
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TestGeneration.addSuites(env.map(rv64udNoDiv))
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if (cfg.divSqrt) {
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TestGeneration.addSuites(env.map(rv64uf))
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TestGeneration.addSuites(env.map(rv64ud))
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}
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}
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if (site(UseAtomics)) TestGeneration.addSuites(env.map(if (site(XLen) == 64) rv64ua else rv32ua))
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if (site(UseCompressed)) TestGeneration.addSuites(env.map(if (site(XLen) == 64) rv64uc else rv32uc))
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val (rvi, rvu) =
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if (site(XLen) == 64) ((if (site(UseVM)) rv64i else rv64pi), rv64u)
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else ((if (site(UseVM)) rv32i else rv32pi), rv32u)
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TestGeneration.addSuites(rvi.map(_("p")))
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TestGeneration.addSuites((if(site(UseVM)) List("v") else List()).flatMap(env => rvu.map(_(env))))
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TestGeneration.addSuite(if (site(UseVM)) benchmarks else emptyBmarks)
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List.fill(site(NTiles)){ (r: Bool, p: Parameters) =>
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Module(new RocketTile(resetSignal = r)(p.alterPartial({
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case TLId => "L1toL2"
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case NUncachedTileLinkPorts => 1 + site(RoccNMemChannels)
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})))
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}
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}
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case BuildRoCC => Nil
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case RoccNMemChannels => site(BuildRoCC).map(_.nMemChannels).foldLeft(0)(_ + _)
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case RoccNPTWPorts => site(BuildRoCC).map(_.nPTWPorts).foldLeft(0)(_ + _)
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//Rocket Core Constants
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case CoreInstBits => if (site(UseCompressed)) 16 else 32
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case FetchWidth => if (site(UseCompressed)) 2 else 1
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case RetireWidth => 1
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case UseVM => true
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case UseUser => true
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case UseDebug => true
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case NBreakpoints => 1
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case FastLoadWord => true
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case FastLoadByte => false
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case XLen => 64
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case FPUKey => Some(FPUConfig())
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case MulDivKey => Some(MulDivConfig())
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case UseAtomics => true
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case UseCompressed => true
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case PLICKey => PLICConfig(site(NTiles), site(UseVM), site(NExtInterrupts), 0)
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case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen))
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case NCustomMRWCSRs => 0
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case ResetVector => BigInt(0x1000)
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case MtvecInit => BigInt(0x1010)
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case MtvecWritable => true
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//Uncore Paramters
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case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
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case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients
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case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) +
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log2Up(site(TLKey(site(TLId))).nClients)
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case TLKey("L1toL2") => {
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val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
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TileLinkParameters(
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coherencePolicy = (
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if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
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else new MESICoherence(site(L2DirectoryRepresentation))),
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nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1 /* MMIO */,
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nCachingClients = site(NCachedTileLinkPorts),
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nCachelessClients = site(NExternalClients) + site(NUncachedTileLinkPorts),
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maxClientXacts = max_int(
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// L1 cache
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site(DCacheKey).nMSHRs + 1 /* IOMSHR */,
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// RoCC
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if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
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maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2,
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maxManagerXacts = site(NAcquireTransactors) + 2,
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dataBeats = innerDataBeats,
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dataBits = site(CacheBlockBytes)*8)
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}
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case TLKey("L2toMC") =>
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TileLinkParameters(
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coherencePolicy = new MEICoherence(
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new NullRepresentation(site(NBanksPerMemoryChannel))),
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nManagers = 1,
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nCachingClients = site(NBanksPerMemoryChannel),
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nCachelessClients = 0,
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maxClientXacts = 1,
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maxClientsPerPort = site(NAcquireTransactors) + 2,
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maxManagerXacts = 1,
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dataBeats = innerDataBeats,
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dataBits = site(CacheBlockBytes)*8)
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case TLKey("Outermost") => site(TLKey("L2toMC")).copy(
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maxClientXacts = site(NAcquireTransactors) + 2,
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maxClientsPerPort = site(NBanksPerMemoryChannel),
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dataBeats = site(MIFDataBeats))
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case TLKey("L2toMMIO") => {
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TileLinkParameters(
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coherencePolicy = new MICoherence(
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new NullRepresentation(site(NBanksPerMemoryChannel))),
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nManagers = site(GlobalAddrMap).subMap("io").numSlaves,
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nCachingClients = 0,
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nCachelessClients = 1,
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maxClientXacts = 4,
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maxClientsPerPort = 1,
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maxManagerXacts = 1,
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dataBeats = innerDataBeats,
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dataBits = site(CacheBlockBytes) * 8)
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}
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case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
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case BootROMFile => "./bootrom/bootrom.img"
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case NTiles => Knob("NTILES")
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case NBanksPerMemoryChannel => Knob("NBANKS_PER_MEM_CHANNEL")
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case BankIdLSB => 0
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case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64)
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case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
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case EnableL2Logging => false
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case ExtraCoreplexPorts => (p: Parameters) => new Bundle
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case RegressionTestNames => LinkedHashSet(
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"rv64ud-v-fcvt",
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"rv64ud-p-fdiv",
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"rv64ud-v-fadd",
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"rv64uf-v-fadd",
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"rv64um-v-mul",
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"rv64mi-p-breakpoint",
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"rv64uc-v-rvc",
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"rv64ud-v-structural",
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"rv64si-p-wfi",
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"rv64um-v-divw",
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"rv64ua-v-lrsc",
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"rv64ui-v-fence_i",
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"rv64ud-v-fcvt_w",
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"rv64uf-v-fmin",
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"rv64ui-v-sb",
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"rv64ua-v-amomax_d",
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"rv64ud-v-move",
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"rv64ud-v-fclass",
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"rv64ua-v-amoand_d",
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"rv64ua-v-amoxor_d",
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"rv64si-p-sbreak",
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"rv64ud-v-fmadd",
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"rv64uf-v-ldst",
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"rv64um-v-mulh",
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"rv64si-p-dirty")
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case _ => throw new CDEMatchError
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}},
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knobValues = {
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case "NTILES" => 1
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case "NBANKS_PER_MEM_CHANNEL" => 1
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case "L1D_MSHRS" => 2
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case "L1D_SETS" => 64
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case "L1D_WAYS" => 4
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case "L1I_SETS" => 64
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case "L1I_WAYS" => 4
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case _ => throw new CDEMatchError
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}
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)
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class WithNCores(n: Int) extends Config(
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knobValues = { case"NTILES" => n; case _ => throw new CDEMatchError })
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class WithNBanksPerMemChannel(n: Int) extends Config(
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knobValues = {
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case "NBANKS_PER_MEM_CHANNEL" => n
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case _ => throw new CDEMatchError
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})
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class WithL2Cache extends Config(
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(pname,site,here) => pname match {
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case "L2_CAPACITY_IN_KB" => Knob("L2_CAPACITY_IN_KB")
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case "L2Bank" => {
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case NSets => (((here[Int]("L2_CAPACITY_IN_KB")*1024) /
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site(CacheBlockBytes)) /
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(site(NBanksPerMemoryChannel)*site(NMemoryChannels))) /
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site(NWays)
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case NWays => Knob("L2_WAYS")
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case RowBits => site(TLKey(site(TLId))).dataBitsPerBeat
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case CacheIdBits => log2Ceil(site(NMemoryChannels) * site(NBanksPerMemoryChannel))
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case SplitMetadata => Knob("L2_SPLIT_METADATA")
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}: PartialFunction[Any,Any]
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case NAcquireTransactors => 2
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case NSecondaryMisses => 4
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case L2DirectoryRepresentation => new FullRepresentation(site(NTiles))
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case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
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Module(new L2HellaCacheBank()(p.alterPartial({
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case CacheId => id
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case CacheName => "L2Bank"
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMC"})))
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case L2Replacer => () => new SeqRandom(site(NWays))
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case _ => throw new CDEMatchError
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},
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knobValues = { case "L2_WAYS" => 8; case "L2_CAPACITY_IN_KB" => 2048; case "L2_SPLIT_METADATA" => false; case _ => throw new CDEMatchError }
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)
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class WithBufferlessBroadcastHub extends Config(
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(pname, site, here) => pname match {
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case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
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Module(new BufferlessBroadcastHub()(p.alterPartial({
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMC" })))
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})
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/**
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* WARNING!!! IGNORE AT YOUR OWN PERIL!!!
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*
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* There is a very restrictive set of conditions under which the stateless
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* bridge will function properly. There can only be a single tile. This tile
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* MUST use the blocking data cache (L1D_MSHRS == 0) and MUST NOT have an
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* uncached channel capable of writes (i.e. a RoCC accelerator).
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*
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* This is because the stateless bridge CANNOT generate probes, so if your
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* system depends on coherence between channels in any way,
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* DO NOT use this configuration.
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*/
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class WithStatelessBridge extends Config (
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topDefinitions = (pname, site, here) => pname match {
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case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
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Module(new ManagerToClientStatelessBridge()(p.alterPartial({
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMC" })))
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},
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knobValues = {
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case "L1D_MSHRS" => 0
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case _ => throw new CDEMatchError
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}
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)
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class WithPLRU extends Config(
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(pname, site, here) => pname match {
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case L2Replacer => () => new SeqPLRU(site(NSets), site(NWays))
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case _ => throw new CDEMatchError
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})
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class WithL2Capacity(size_kb: Int) extends Config(
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knobValues = {
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case "L2_CAPACITY_IN_KB" => size_kb
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case _ => throw new CDEMatchError
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})
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class WithNL2Ways(n: Int) extends Config(
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knobValues = {
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case "L2_WAYS" => n
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case _ => throw new CDEMatchError
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})
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class WithRV32 extends Config(
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(pname,site,here) => pname match {
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case XLen => 32
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case UseVM => false
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case UseUser => false
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case UseAtomics => false
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case FPUKey => None
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case RegressionTestNames => LinkedHashSet(
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"rv32mi-p-ma_addr",
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"rv32mi-p-csr",
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"rv32ui-p-sh",
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"rv32ui-p-lh",
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"rv32mi-p-sbreak",
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"rv32ui-p-sll")
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case _ => throw new CDEMatchError
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}
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)
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class WithBlockingL1 extends Config (
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knobValues = {
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case "L1D_MSHRS" => 0
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case _ => throw new CDEMatchError
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}
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)
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class WithSmallCores extends Config (
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topDefinitions = { (pname,site,here) => pname match {
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case FPUKey => None
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case NTLBEntries => 4
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case BtbKey => BtbParameters(nEntries = 0)
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case NAcquireTransactors => 2
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case _ => throw new CDEMatchError
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}},
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knobValues = {
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case "L1D_SETS" => 64
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case "L1D_WAYS" => 1
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case "L1I_SETS" => 64
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case "L1I_WAYS" => 1
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case "L1D_MSHRS" => 0
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case _ => throw new CDEMatchError
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}
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)
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class WithRoccExample extends Config(
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(pname, site, here) => pname match {
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case BuildRoCC => Seq(
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RoccParameters(
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opcodes = OpcodeSet.custom0,
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generator = (p: Parameters) => Module(new AccumulatorExample()(p))),
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RoccParameters(
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opcodes = OpcodeSet.custom1,
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generator = (p: Parameters) => Module(new TranslatorExample()(p)),
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nPTWPorts = 1),
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RoccParameters(
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opcodes = OpcodeSet.custom2,
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generator = (p: Parameters) => Module(new CharacterCountExample()(p))))
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case RoccMaxTaggedMemXacts => 1
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case _ => throw new CDEMatchError
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})
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class WithSplitL2Metadata extends Config(
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knobValues = { case "L2_SPLIT_METADATA" => true; case _ => throw new CDEMatchError })
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283
src/main/scala/coreplex/Coreplex.scala
Normal file
283
src/main/scala/coreplex/Coreplex.scala
Normal file
@ -0,0 +1,283 @@
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package coreplex
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||||
|
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import Chisel._
|
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import cde.{Parameters, Field}
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import junctions._
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import uncore.tilelink._
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import uncore.coherence._
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import uncore.agents._
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import uncore.devices._
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import uncore.util._
|
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import uncore.converters._
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import rocket._
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||||
import rocket.Util._
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import java.nio.{ByteBuffer,ByteOrder}
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import java.nio.file.{Files, Paths}
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/** Number of memory channels */
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case object NMemoryChannels extends Field[Int]
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/** Number of banks per memory channel */
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case object NBanksPerMemoryChannel extends Field[Int]
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/** Least significant bit of address used for bank partitioning */
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case object BankIdLSB extends Field[Int]
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/** Function for building some kind of coherence manager agent */
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case object BuildL2CoherenceManager extends Field[(Int, Parameters) => CoherenceAgent]
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/** Function for building some kind of tile connected to a reset signal */
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case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
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/** A string describing on-chip devices, readable by target software */
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case object ConfigString extends Field[Array[Byte]]
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/** Number of external interrupt sources */
|
||||
case object NExtInterrupts extends Field[Int]
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||||
/** Interrupt controller configuration */
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||||
case object PLICKey extends Field[PLICConfig]
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||||
/** Number of clock cycles per RTC tick */
|
||||
case object RTCPeriod extends Field[Int]
|
||||
/** The file to read the BootROM contents from */
|
||||
case object BootROMFile extends Field[String]
|
||||
/** Export an external MMIO slave port */
|
||||
case object ExportMMIOPort extends Field[Boolean]
|
||||
/** Expose additional TileLink client ports */
|
||||
case object NExternalClients extends Field[Int]
|
||||
/** Extra top-level ports exported from the coreplex */
|
||||
case object ExtraCoreplexPorts extends Field[Parameters => Bundle]
|
||||
|
||||
trait HasCoreplexParameters {
|
||||
implicit val p: Parameters
|
||||
lazy val nTiles = p(NTiles)
|
||||
lazy val nCachedTilePorts = p(NCachedTileLinkPorts)
|
||||
lazy val nUncachedTilePorts = p(NUncachedTileLinkPorts)
|
||||
lazy val nMemChannels = p(NMemoryChannels)
|
||||
lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
|
||||
lazy val nBanks = nMemChannels*nBanksPerMemChannel
|
||||
lazy val lsb = p(BankIdLSB)
|
||||
lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
|
||||
lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" })
|
||||
lazy val outermostMMIOParams = p.alterPartial({ case TLId => "MMIO_Outermost" })
|
||||
lazy val nExtClients = p(NExternalClients)
|
||||
lazy val exportMMIO = p(ExportMMIOPort)
|
||||
}
|
||||
|
||||
/** Wrapper around everything that isn't a Tile.
|
||||
*
|
||||
* Usually this is clocked and/or place-and-routed separately from the Tiles.
|
||||
*/
|
||||
class Uncore(implicit val p: Parameters) extends Module
|
||||
with HasCoreplexParameters {
|
||||
|
||||
val io = new Bundle {
|
||||
val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))
|
||||
val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
|
||||
val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
|
||||
val ext_uncached = Vec(nExtClients, new ClientUncachedTileLinkIO()(innerParams)).flip
|
||||
val prci = Vec(nTiles, new PRCITileIO).asOutput
|
||||
val mmio = if (exportMMIO) Some(new ClientUncachedTileLinkIO()(outermostMMIOParams)) else None
|
||||
val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
|
||||
val debug = new DebugBusIO()(p).flip
|
||||
}
|
||||
|
||||
val outmemsys = if (nCachedTilePorts + nUncachedTilePorts > 0)
|
||||
Module(new DefaultOuterMemorySystem) // NoC, LLC and SerDes
|
||||
else Module(new DummyOuterMemorySystem)
|
||||
outmemsys.io.incoherent foreach (_ := false)
|
||||
outmemsys.io.tiles_uncached <> io.tiles_uncached
|
||||
outmemsys.io.tiles_cached <> io.tiles_cached
|
||||
outmemsys.io.ext_uncached <> io.ext_uncached
|
||||
io.mem <> outmemsys.io.mem
|
||||
|
||||
buildMMIONetwork(p.alterPartial({case TLId => "L2toMMIO"}))
|
||||
|
||||
def makeBootROM()(implicit p: Parameters) = {
|
||||
val romdata = Files.readAllBytes(Paths.get(p(BootROMFile)))
|
||||
val rom = ByteBuffer.wrap(romdata)
|
||||
|
||||
rom.order(ByteOrder.LITTLE_ENDIAN)
|
||||
|
||||
// for now, have the reset vector jump straight to memory
|
||||
val resetToMemDist = p(GlobalAddrMap)("mem").start - p(ResetVector)
|
||||
require(resetToMemDist == (resetToMemDist.toInt >> 12 << 12))
|
||||
val configStringAddr = p(ResetVector).toInt + rom.capacity
|
||||
|
||||
require(rom.getInt(12) == 0,
|
||||
"Config string address position should not be occupied by code")
|
||||
rom.putInt(12, configStringAddr)
|
||||
rom.array() ++ p(ConfigString).toSeq
|
||||
}
|
||||
|
||||
def buildMMIONetwork(implicit p: Parameters) = {
|
||||
val ioAddrMap = p(GlobalAddrMap).subMap("io")
|
||||
|
||||
val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap))
|
||||
mmioNetwork.io.in.head <> outmemsys.io.mmio
|
||||
|
||||
val plic = Module(new PLIC(p(PLICKey)))
|
||||
plic.io.tl <> mmioNetwork.port("int:plic")
|
||||
for (i <- 0 until io.interrupts.size) {
|
||||
val gateway = Module(new LevelGateway)
|
||||
gateway.io.interrupt := io.interrupts(i)
|
||||
plic.io.devices(i) <> gateway.io.plic
|
||||
}
|
||||
|
||||
val debugModule = Module(new DebugModule)
|
||||
debugModule.io.tl <> mmioNetwork.port("int:debug")
|
||||
debugModule.io.db <> io.debug
|
||||
|
||||
val prci = Module(new PRCI)
|
||||
prci.io.tl <> mmioNetwork.port("int:prci")
|
||||
io.prci := prci.io.tiles
|
||||
prci.io.rtcTick := Counter(p(RTCPeriod)).inc() // placeholder for real RTC
|
||||
|
||||
for (i <- 0 until nTiles) {
|
||||
prci.io.interrupts(i).meip := plic.io.harts(plic.cfg.context(i, 'M'))
|
||||
if (p(UseVM))
|
||||
prci.io.interrupts(i).seip := plic.io.harts(plic.cfg.context(i, 'S'))
|
||||
prci.io.interrupts(i).debug := debugModule.io.debugInterrupts(i)
|
||||
|
||||
io.prci(i).reset := reset
|
||||
}
|
||||
|
||||
val bootROM = Module(new ROMSlave(makeBootROM()))
|
||||
bootROM.io <> mmioNetwork.port("int:bootrom")
|
||||
|
||||
io.mmio.map { ext => ext <> mmioNetwork.port("ext") }
|
||||
}
|
||||
}
|
||||
|
||||
abstract class OuterMemorySystem(implicit val p: Parameters)
|
||||
extends Module with HasCoreplexParameters {
|
||||
val io = new Bundle {
|
||||
val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
|
||||
val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
|
||||
val ext_uncached = Vec(nExtClients, new ClientUncachedTileLinkIO()(innerParams)).flip
|
||||
val incoherent = Vec(nCachedTilePorts, Bool()).asInput
|
||||
val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))
|
||||
val mmio = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => "L2toMMIO"}))
|
||||
}
|
||||
}
|
||||
|
||||
/** Use in place of OuterMemorySystem if there are no clients to connect. */
|
||||
class DummyOuterMemorySystem(implicit p: Parameters) extends OuterMemorySystem()(p) {
|
||||
require(nCachedTilePorts + nUncachedTilePorts + nExtClients == 0)
|
||||
|
||||
io.mem.foreach { tl =>
|
||||
tl.acquire.valid := Bool(false)
|
||||
tl.grant.ready := Bool(false)
|
||||
}
|
||||
|
||||
io.mmio.acquire.valid := Bool(false)
|
||||
io.mmio.grant.ready := Bool(false)
|
||||
}
|
||||
|
||||
/** The whole outer memory hierarchy, including a NoC, some kind of coherence
|
||||
* manager agent, and a converter from TileLink to MemIO.
|
||||
*/
|
||||
class DefaultOuterMemorySystem(implicit p: Parameters) extends OuterMemorySystem()(p) {
|
||||
// Create a simple L1toL2 NoC between the tiles and the banks of outer memory
|
||||
// Cached ports are first in client list, making sharerToClientId just an indentity function
|
||||
// addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
|
||||
def sharerToClientId(sharerId: UInt) = sharerId
|
||||
def addrToBank(addr: UInt): UInt = {
|
||||
val isMemory = p(GlobalAddrMap).isInRegion("mem", addr << log2Up(p(CacheBlockBytes)))
|
||||
Mux(isMemory,
|
||||
if (nBanks > 1) addr(lsb + log2Up(nBanks) - 1, lsb) else UInt(0),
|
||||
UInt(nBanks))
|
||||
}
|
||||
val preBuffering = TileLinkDepths(1,1,2,2,0)
|
||||
val l1tol2net = Module(new PortedTileLinkCrossbar(addrToBank, sharerToClientId, preBuffering))
|
||||
|
||||
// Create point(s) of coherence serialization
|
||||
val managerEndpoints = List.tabulate(nBanks){id => p(BuildL2CoherenceManager)(id, p)}
|
||||
managerEndpoints.foreach { _.incoherent := io.incoherent }
|
||||
|
||||
val mmioManager = Module(new MMIOTileLinkManager()(p.alterPartial({
|
||||
case TLId => "L1toL2"
|
||||
case InnerTLId => "L1toL2"
|
||||
case OuterTLId => "L2toMMIO"
|
||||
})))
|
||||
io.mmio <> mmioManager.io.outer
|
||||
|
||||
// Wire the tiles to the TileLink client ports of the L1toL2 network,
|
||||
// and coherence manager(s) to the other side
|
||||
l1tol2net.io.clients_cached <> io.tiles_cached
|
||||
l1tol2net.io.clients_uncached <> io.tiles_uncached ++ io.ext_uncached
|
||||
l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner
|
||||
|
||||
// Create a converter between TileLinkIO and MemIO for each channel
|
||||
val outerTLParams = p.alterPartial({ case TLId => "L2toMC" })
|
||||
val backendBuffering = TileLinkDepths(0,0,0,0,0)
|
||||
|
||||
// TODO: the code to print this stuff should live somewhere else
|
||||
println("Generated Address Map")
|
||||
for (entry <- p(GlobalAddrMap).flatten) {
|
||||
val name = entry.name
|
||||
val start = entry.region.start
|
||||
val end = entry.region.start + entry.region.size - 1
|
||||
println(f"\t$name%s $start%x - $end%x")
|
||||
}
|
||||
println("Generated Configuration String")
|
||||
println(new String(p(ConfigString)))
|
||||
|
||||
val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, nMemChannels)(outermostParams))
|
||||
|
||||
for ((bank, icPort) <- managerEndpoints zip mem_ic.io.in) {
|
||||
val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
|
||||
unwrap.io.in <> ClientTileLinkEnqueuer(bank.outerTL, backendBuffering)(outerTLParams)
|
||||
TileLinkWidthAdapter(icPort, unwrap.io.out)
|
||||
}
|
||||
|
||||
io.mem <> mem_ic.io.out
|
||||
}
|
||||
|
||||
abstract class Coreplex(implicit val p: Parameters) extends Module
|
||||
with HasCoreplexParameters {
|
||||
class CoreplexIO(implicit val p: Parameters) extends Bundle {
|
||||
val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))
|
||||
val ext_clients = Vec(nExtClients, new ClientUncachedTileLinkIO()(innerParams)).flip
|
||||
val mmio = if(p(ExportMMIOPort)) Some(new ClientUncachedTileLinkIO()(outermostMMIOParams)) else None
|
||||
val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
|
||||
val debug = new DebugBusIO()(p).flip
|
||||
val extra = p(ExtraCoreplexPorts)(p)
|
||||
val success: Option[Bool] = if (hasSuccessFlag) Some(Bool(OUTPUT)) else None
|
||||
}
|
||||
|
||||
def hasSuccessFlag: Boolean = false
|
||||
val io = new CoreplexIO
|
||||
}
|
||||
|
||||
class DefaultCoreplex(topParams: Parameters) extends Coreplex()(topParams) {
|
||||
// Build an Uncore and a set of Tiles
|
||||
val tileResets = Wire(Vec(nTiles, Bool()))
|
||||
val tileList = p(BuildTiles).zip(tileResets).map {
|
||||
case (tile, rst) => tile(rst, p)
|
||||
}
|
||||
val nCachedPorts = tileList.map(tile => tile.io.cached.size).reduce(_ + _)
|
||||
val nUncachedPorts = tileList.map(tile => tile.io.uncached.size).reduce(_ + _)
|
||||
|
||||
val innerTLParams = p.alterPartial({
|
||||
case HastiId => "TL"
|
||||
case TLId => "L1toL2"
|
||||
case NCachedTileLinkPorts => nCachedPorts
|
||||
case NUncachedTileLinkPorts => nUncachedPorts
|
||||
})
|
||||
|
||||
val uncore = Module(new Uncore()(innerTLParams))
|
||||
|
||||
(uncore.io.prci, tileResets, tileList).zipped.foreach {
|
||||
case (prci, rst, tile) =>
|
||||
rst := prci.reset
|
||||
tile.io.prci <> prci
|
||||
}
|
||||
|
||||
// Connect the uncore to the tile memory ports, HostIO and MemIO
|
||||
uncore.io.tiles_cached <> tileList.map(_.io.cached).flatten
|
||||
uncore.io.tiles_uncached <> tileList.map(_.io.uncached).flatten
|
||||
uncore.io.interrupts <> io.interrupts
|
||||
uncore.io.debug <> io.debug
|
||||
uncore.io.ext_uncached <> io.ext_clients
|
||||
if (exportMMIO) { io.mmio.get <> uncore.io.mmio.get }
|
||||
io.mem <> uncore.io.mem
|
||||
}
|
||||
|
||||
class GroundTestCoreplex(topParams: Parameters) extends DefaultCoreplex(topParams) {
|
||||
override def hasSuccessFlag = true
|
||||
io.success.get := tileList.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
|
||||
}
|
||||
62
src/main/scala/coreplex/DirectGroundTest.scala
Normal file
62
src/main/scala/coreplex/DirectGroundTest.scala
Normal file
@ -0,0 +1,62 @@
|
||||
package coreplex
|
||||
|
||||
import Chisel._
|
||||
import cde.{Parameters, Field}
|
||||
import groundtest._
|
||||
import uncore.tilelink._
|
||||
import uncore.agents._
|
||||
|
||||
case object ExportGroundTestStatus extends Field[Boolean]
|
||||
|
||||
class DirectGroundTestCoreplex(topParams: Parameters) extends Coreplex()(topParams) {
|
||||
// Not using the debug
|
||||
io.debug.req.ready := Bool(false)
|
||||
io.debug.resp.valid := Bool(false)
|
||||
|
||||
require(!exportMMIO)
|
||||
require(nExtClients == 0)
|
||||
require(nMemChannels == 1)
|
||||
require(nTiles == 1)
|
||||
|
||||
val test = p(BuildGroundTest)(outermostParams.alterPartial({
|
||||
case GroundTestId => 0
|
||||
case CacheName => "L1D"
|
||||
}))
|
||||
require(test.io.cache.size == 0)
|
||||
require(test.io.mem.size == nBanksPerMemChannel)
|
||||
require(test.io.ptw.size == 0)
|
||||
|
||||
val mem_ic = Module(new TileLinkMemoryInterconnect(
|
||||
nBanksPerMemChannel, nMemChannels)(outermostParams))
|
||||
|
||||
mem_ic.io.in <> test.io.mem
|
||||
io.mem <> mem_ic.io.out
|
||||
|
||||
if (p(ExportGroundTestStatus)) {
|
||||
val status = io.extra.asInstanceOf[GroundTestStatus]
|
||||
|
||||
val s_running :: s_finished :: s_errored :: s_timeout :: Nil = Enum(Bits(), 4)
|
||||
val state = Reg(init = s_running)
|
||||
val error_code = Reg(status.error.bits)
|
||||
val timeout_code = Reg(status.timeout.bits)
|
||||
when (state === s_running) {
|
||||
when (test.io.status.finished) { state := s_finished }
|
||||
when (test.io.status.error.valid) {
|
||||
state := s_errored
|
||||
error_code := test.io.status.error.bits
|
||||
}
|
||||
when (test.io.status.timeout.valid) {
|
||||
state := s_timeout
|
||||
timeout_code := test.io.status.timeout.bits
|
||||
}
|
||||
}
|
||||
status.finished := (state === s_finished)
|
||||
status.error.valid := (state === s_errored)
|
||||
status.error.bits := error_code
|
||||
status.timeout.valid := (state === s_timeout)
|
||||
status.timeout.bits := timeout_code
|
||||
}
|
||||
|
||||
override def hasSuccessFlag = true
|
||||
io.success.get := test.io.status.finished
|
||||
}
|
||||
200
src/main/scala/coreplex/TestConfigs.scala
Normal file
200
src/main/scala/coreplex/TestConfigs.scala
Normal file
@ -0,0 +1,200 @@
|
||||
package coreplex
|
||||
|
||||
import Chisel._
|
||||
import groundtest._
|
||||
import rocket._
|
||||
import uncore.tilelink._
|
||||
import uncore.coherence._
|
||||
import uncore.agents._
|
||||
import uncore.devices.NTiles
|
||||
import uncore.unittests._
|
||||
import junctions._
|
||||
import junctions.unittests._
|
||||
import scala.collection.mutable.LinkedHashSet
|
||||
import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
|
||||
import scala.math.max
|
||||
import ConfigUtils._
|
||||
|
||||
class WithComparator extends Config(
|
||||
(pname, site, here) => pname match {
|
||||
case GroundTestKey => Seq.fill(site(NTiles)) {
|
||||
GroundTestTileSettings(uncached = site(ComparatorKey).targets.size)
|
||||
}
|
||||
case BuildGroundTest =>
|
||||
(p: Parameters) => Module(new ComparatorCore()(p))
|
||||
case ComparatorKey => ComparatorParameters(
|
||||
targets = Seq("mem", "io:ext:testram").map(name =>
|
||||
site(GlobalAddrMap)(name).start.longValue),
|
||||
width = 8,
|
||||
operations = 1000,
|
||||
atomics = site(UseAtomics),
|
||||
prefetches = site("COMPARATOR_PREFETCHES"))
|
||||
case FPUConfig => None
|
||||
case UseAtomics => false
|
||||
case "COMPARATOR_PREFETCHES" => false
|
||||
case _ => throw new CDEMatchError
|
||||
})
|
||||
|
||||
class WithAtomics extends Config(
|
||||
(pname, site, here) => pname match {
|
||||
case UseAtomics => true
|
||||
case _ => throw new CDEMatchError
|
||||
})
|
||||
|
||||
class WithPrefetches extends Config(
|
||||
(pname, site, here) => pname match {
|
||||
case "COMPARATOR_PREFETCHES" => true
|
||||
case _ => throw new CDEMatchError
|
||||
})
|
||||
|
||||
class WithMemtest extends Config(
|
||||
(pname, site, here) => pname match {
|
||||
case GroundTestKey => Seq.fill(site(NTiles)) {
|
||||
GroundTestTileSettings(1, 1)
|
||||
}
|
||||
case GeneratorKey => GeneratorParameters(
|
||||
maxRequests = 128,
|
||||
startAddress = site(GlobalAddrMap)("mem").start)
|
||||
case BuildGroundTest =>
|
||||
(p: Parameters) => Module(new GeneratorTest()(p))
|
||||
case _ => throw new CDEMatchError
|
||||
})
|
||||
|
||||
class WithNGenerators(nUncached: Int, nCached: Int) extends Config(
|
||||
(pname, site, here) => pname match {
|
||||
case GroundTestKey => Seq.fill(site(NTiles)) {
|
||||
GroundTestTileSettings(nUncached, nCached)
|
||||
}
|
||||
case _ => throw new CDEMatchError
|
||||
})
|
||||
|
||||
class WithCacheFillTest extends Config(
|
||||
(pname, site, here) => pname match {
|
||||
case GroundTestKey => Seq.fill(site(NTiles)) {
|
||||
GroundTestTileSettings(uncached = 1)
|
||||
}
|
||||
case BuildGroundTest =>
|
||||
(p: Parameters) => Module(new CacheFillTest()(p))
|
||||
case _ => throw new CDEMatchError
|
||||
},
|
||||
knobValues = {
|
||||
case "L2_WAYS" => 4
|
||||
case "L2_CAPACITY_IN_KB" => 4
|
||||
case _ => throw new CDEMatchError
|
||||
})
|
||||
|
||||
class WithBroadcastRegressionTest extends Config(
|
||||
(pname, site, here) => pname match {
|
||||
case GroundTestKey => Seq.fill(site(NTiles)) {
|
||||
GroundTestTileSettings(1, 1, maxXacts = 3)
|
||||
}
|
||||
case BuildGroundTest =>
|
||||
(p: Parameters) => Module(new RegressionTest()(p))
|
||||
case GroundTestRegressions =>
|
||||
(p: Parameters) => RegressionTests.broadcastRegressions(p)
|
||||
case _ => throw new CDEMatchError
|
||||
})
|
||||
|
||||
class WithCacheRegressionTest extends Config(
|
||||
(pname, site, here) => pname match {
|
||||
case GroundTestKey => Seq.fill(site(NTiles)) {
|
||||
GroundTestTileSettings(1, 1, maxXacts = 5)
|
||||
}
|
||||
case BuildGroundTest =>
|
||||
(p: Parameters) => Module(new RegressionTest()(p))
|
||||
case GroundTestRegressions =>
|
||||
(p: Parameters) => RegressionTests.cacheRegressions(p)
|
||||
case _ => throw new CDEMatchError
|
||||
})
|
||||
|
||||
class WithNastiConverterTest extends Config(
|
||||
(pname, site, here) => pname match {
|
||||
case GroundTestKey => Seq.fill(site(NTiles)) {
|
||||
GroundTestTileSettings(uncached = 1)
|
||||
}
|
||||
case GeneratorKey => GeneratorParameters(
|
||||
maxRequests = 128,
|
||||
startAddress = site(GlobalAddrMap)("mem").start)
|
||||
case BuildGroundTest =>
|
||||
(p: Parameters) => Module(new NastiConverterTest()(p))
|
||||
case _ => throw new CDEMatchError
|
||||
})
|
||||
|
||||
class WithTraceGen extends Config(
|
||||
topDefinitions = (pname, site, here) => pname match {
|
||||
case GroundTestKey => Seq.fill(site(NTiles)) {
|
||||
GroundTestTileSettings(uncached = 1, cached = 1)
|
||||
}
|
||||
case BuildGroundTest =>
|
||||
(p: Parameters) => Module(new GroundTestTraceGenerator()(p))
|
||||
case GeneratorKey => GeneratorParameters(
|
||||
maxRequests = 256,
|
||||
startAddress = 0)
|
||||
case AddressBag => {
|
||||
val nSets = 32 // L2 NSets
|
||||
val nWays = 1
|
||||
val blockOffset = site(CacheBlockOffsetBits)
|
||||
val baseAddr = site(GlobalAddrMap)("mem").start
|
||||
val nBeats = site(MIFDataBeats)
|
||||
List.tabulate(4 * nWays) { i =>
|
||||
Seq.tabulate(nBeats) { j => (j * 8) + ((i * nSets) << blockOffset) }
|
||||
}.flatten.map(addr => baseAddr + BigInt(addr))
|
||||
}
|
||||
case UseAtomics => true
|
||||
case _ => throw new CDEMatchError
|
||||
},
|
||||
knobValues = {
|
||||
case "L1D_SETS" => 16
|
||||
case "L1D_WAYS" => 1
|
||||
})
|
||||
|
||||
class WithPCIeMockupTest extends Config(
|
||||
(pname, site, here) => pname match {
|
||||
case NTiles => 2
|
||||
case GroundTestKey => Seq(
|
||||
GroundTestTileSettings(1, 1),
|
||||
GroundTestTileSettings(1))
|
||||
case GeneratorKey => GeneratorParameters(
|
||||
maxRequests = 128,
|
||||
startAddress = site(GlobalAddrMap)("mem").start)
|
||||
case BuildGroundTest =>
|
||||
(p: Parameters) => {
|
||||
val id = p(GroundTestId)
|
||||
if (id == 0) Module(new GeneratorTest()(p))
|
||||
else Module(new NastiConverterTest()(p))
|
||||
}
|
||||
case _ => throw new CDEMatchError
|
||||
})
|
||||
|
||||
class WithDirectMemtest extends Config(
|
||||
(pname, site, here) => {
|
||||
val nGens = 8
|
||||
pname match {
|
||||
case GroundTestKey => Seq(GroundTestTileSettings(uncached = nGens))
|
||||
case GeneratorKey => GeneratorParameters(
|
||||
maxRequests = 1024,
|
||||
startAddress = 0)
|
||||
case BuildGroundTest =>
|
||||
(p: Parameters) => Module(new GeneratorTest()(p))
|
||||
case _ => throw new CDEMatchError
|
||||
}
|
||||
})
|
||||
|
||||
class WithDirectComparator extends Config(
|
||||
(pname, site, here) => pname match {
|
||||
case GroundTestKey => Seq.fill(site(NTiles)) {
|
||||
GroundTestTileSettings(uncached = site(ComparatorKey).targets.size)
|
||||
}
|
||||
case BuildGroundTest =>
|
||||
(p: Parameters) => Module(new ComparatorCore()(p))
|
||||
case ComparatorKey => ComparatorParameters(
|
||||
targets = Seq(0L, 0x100L),
|
||||
width = 8,
|
||||
operations = 1000,
|
||||
atomics = site(UseAtomics),
|
||||
prefetches = site("COMPARATOR_PREFETCHES"))
|
||||
case FPUConfig => None
|
||||
case UseAtomics => false
|
||||
case "COMPARATOR_PREFETCHES" => false
|
||||
case _ => throw new CDEMatchError
|
||||
})
|
||||
186
src/main/scala/coreplex/Testing.scala
Normal file
186
src/main/scala/coreplex/Testing.scala
Normal file
@ -0,0 +1,186 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
package coreplex
|
||||
|
||||
import Chisel._
|
||||
import scala.collection.mutable.{LinkedHashSet,LinkedHashMap}
|
||||
import cde.{Parameters, ParameterDump, Config, Field, CDEMatchError}
|
||||
|
||||
case object RegressionTestNames extends Field[LinkedHashSet[String]]
|
||||
|
||||
abstract class RocketTestSuite {
|
||||
val dir: String
|
||||
val makeTargetName: String
|
||||
val names: LinkedHashSet[String]
|
||||
val envName: String
|
||||
def postScript = s"""
|
||||
|
||||
$$(addprefix $$(output_dir)/, $$(addsuffix .hex, $$($makeTargetName))): $$(output_dir)/%.hex: $dir/%.hex
|
||||
\tmkdir -p $$(output_dir)
|
||||
\tln -fs $$< $$@
|
||||
|
||||
$$(addprefix $$(output_dir)/, $$($makeTargetName)): $$(output_dir)/%: $dir/%
|
||||
\tmkdir -p $$(output_dir)
|
||||
\tln -fs $$< $$@
|
||||
|
||||
run-$makeTargetName: $$(addprefix $$(output_dir)/, $$(addsuffix .out, $$($makeTargetName)))
|
||||
\t@echo; perl -ne 'print " [$$$$1] $$$$ARGV \\t$$$$2\\n" if( /\\*{3}(.{8})\\*{3}(.*)/ || /ASSERTION (FAILED)/i )' $$^ /dev/null | perl -ne 'if(/(.*)/){print "$$$$1\\n\\n"; exit(1) if eof()}'
|
||||
|
||||
run-$makeTargetName-debug: $$(addprefix $$(output_dir)/, $$(addsuffix .vpd, $$($makeTargetName)))
|
||||
\t@echo; perl -ne 'print " [$$$$1] $$$$ARGV \\t$$$$2\\n" if( /\\*{3}(.{8})\\*{3}(.*)/ || /ASSERTION (FAILED)/i )' $$(patsubst %.vpd,%.out,$$^) /dev/null | perl -ne 'if(/(.*)/){print "$$$$1\\n\\n"; exit(1) if eof()}'
|
||||
"""
|
||||
}
|
||||
|
||||
class AssemblyTestSuite(prefix: String, val names: LinkedHashSet[String])(val envName: String) extends RocketTestSuite {
|
||||
val dir = "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa"
|
||||
val makeTargetName = prefix + "-" + envName + "-asm-tests"
|
||||
override def toString = s"$makeTargetName = \\\n" + names.map(n => s"\t$prefix-$envName-$n").mkString(" \\\n") + postScript
|
||||
}
|
||||
|
||||
class BenchmarkTestSuite(makePrefix: String, val dir: String, val names: LinkedHashSet[String]) extends RocketTestSuite {
|
||||
val envName = ""
|
||||
val makeTargetName = makePrefix + "-bmark-tests"
|
||||
override def toString = s"$makeTargetName = \\\n" + names.map(n => s"\t$n.riscv").mkString(" \\\n") + postScript
|
||||
}
|
||||
|
||||
class RegressionTestSuite(val names: LinkedHashSet[String]) extends RocketTestSuite {
|
||||
val envName = ""
|
||||
val dir = "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa"
|
||||
val makeTargetName = "regression-tests"
|
||||
override def toString = s"$makeTargetName = \\\n" + names.mkString(" \\\n")
|
||||
}
|
||||
|
||||
object TestGeneration {
|
||||
import scala.collection.mutable.HashMap
|
||||
val asmSuites = new LinkedHashMap[String,AssemblyTestSuite]()
|
||||
val bmarkSuites = new LinkedHashMap[String,BenchmarkTestSuite]()
|
||||
val regressionSuites = new LinkedHashMap[String,RegressionTestSuite]()
|
||||
|
||||
def addSuite(s: RocketTestSuite) {
|
||||
s match {
|
||||
case a: AssemblyTestSuite => asmSuites += (a.makeTargetName -> a)
|
||||
case b: BenchmarkTestSuite => bmarkSuites += (b.makeTargetName -> b)
|
||||
case r: RegressionTestSuite => regressionSuites += (r.makeTargetName -> r)
|
||||
}
|
||||
}
|
||||
|
||||
def addSuites(s: Seq[RocketTestSuite]) { s.foreach(addSuite) }
|
||||
|
||||
def generateMakefrag(topModuleName: String, configClassName: String) {
|
||||
def gen(kind: String, s: Seq[RocketTestSuite]) = {
|
||||
if(s.length > 0) {
|
||||
val envs = s.groupBy(_.envName)
|
||||
val targets = s.map(t => s"$$(${t.makeTargetName})").mkString(" ")
|
||||
s.map(_.toString).mkString("\n") +
|
||||
envs.filterKeys(_ != "").map( {
|
||||
case (env,envsuites) => {
|
||||
val suites = envsuites.map(t => s"$$(${t.makeTargetName})").mkString(" ")
|
||||
s"""
|
||||
run-$kind-$env-tests: $$(addprefix $$(output_dir)/, $$(addsuffix .out, $suites))
|
||||
\t@echo; perl -ne 'print " [$$$$1] $$$$ARGV \\t$$$$2\\n" if( /\\*{3}(.{8})\\*{3}(.*)/ || /ASSERTION (FAILED)/i )' $$^ /dev/null | perl -ne 'if(/(.*)/){print "$$$$1\\n\\n"; exit(1) if eof()}'
|
||||
run-$kind-$env-tests-debug: $$(addprefix $$(output_dir)/, $$(addsuffix .vpd, $suites))
|
||||
\t@echo; perl -ne 'print " [$$$$1] $$$$ARGV \\t$$$$2\\n" if( /\\*{3}(.{8})\\*{3}(.*)/ || /ASSERTION (FAILED)/i )' $$(patsubst %.vpd,%.out,$$^) /dev/null | perl -ne 'if(/(.*)/){print "$$$$1\\n\\n"; exit(1) if eof()}'
|
||||
run-$kind-$env-tests-fast: $$(addprefix $$(output_dir)/, $$(addsuffix .run, $suites))
|
||||
\t@echo; perl -ne 'print " [$$$$1] $$$$ARGV \\t$$$$2\\n" if( /\\*{3}(.{8})\\*{3}(.*)/ || /ASSERTION (FAILED)/i )' $$^ /dev/null | perl -ne 'if(/(.*)/){print "$$$$1\\n\\n"; exit(1) if eof()}'
|
||||
"""} } ).mkString("\n") + s"""
|
||||
run-$kind-tests: $$(addprefix $$(output_dir)/, $$(addsuffix .out, $targets))
|
||||
\t@echo; perl -ne 'print " [$$$$1] $$$$ARGV \\t$$$$2\\n" if( /\\*{3}(.{8})\\*{3}(.*)/ || /ASSERTION (FAILED)/i )' $$^ /dev/null | perl -ne 'if(/(.*)/){print "$$$$1\\n\\n"; exit(1) if eof()}'
|
||||
run-$kind-tests-debug: $$(addprefix $$(output_dir)/, $$(addsuffix .vpd, $targets))
|
||||
\t@echo; perl -ne 'print " [$$$$1] $$$$ARGV \\t$$$$2\\n" if( /\\*{3}(.{8})\\*{3}(.*)/ || /ASSERTION (FAILED)/i )' $$(patsubst %.vpd,%.out,$$^) /dev/null | perl -ne 'if(/(.*)/){print "$$$$1\\n\\n"; exit(1) if eof()}'
|
||||
run-$kind-tests-fast: $$(addprefix $$(output_dir)/, $$(addsuffix .run, $targets))
|
||||
\t@echo; perl -ne 'print " [$$$$1] $$$$ARGV \\t$$$$2\\n" if( /\\*{3}(.{8})\\*{3}(.*)/ || /ASSERTION (FAILED)/i )' $$^ /dev/null | perl -ne 'if(/(.*)/){print "$$$$1\\n\\n"; exit(1) if eof()}'
|
||||
"""
|
||||
} else { "\n" }
|
||||
}
|
||||
|
||||
val f = createOutputFile(s"$topModuleName.$configClassName.d")
|
||||
f.write(
|
||||
List(
|
||||
gen("asm", asmSuites.values.toSeq),
|
||||
gen("bmark", bmarkSuites.values.toSeq),
|
||||
gen("regression", regressionSuites.values.toSeq)
|
||||
).mkString("\n"))
|
||||
f.close
|
||||
}
|
||||
|
||||
def createOutputFile(name: String) =
|
||||
new java.io.FileWriter(s"${Driver.targetDir}/$name")
|
||||
}
|
||||
|
||||
object DefaultTestSuites {
|
||||
val rv32uiNames = LinkedHashSet(
|
||||
"simple", "add", "addi", "and", "andi", "auipc", "beq", "bge", "bgeu", "blt", "bltu", "bne", "fence_i",
|
||||
"jal", "jalr", "lb", "lbu", "lh", "lhu", "lui", "lw", "or", "ori", "sb", "sh", "sw", "sll", "slli",
|
||||
"slt", "slti", "sra", "srai", "srl", "srli", "sub", "xor", "xori")
|
||||
val rv32ui = new AssemblyTestSuite("rv32ui", rv32uiNames)(_)
|
||||
|
||||
val rv32ucNames = LinkedHashSet("rvc")
|
||||
val rv32uc = new AssemblyTestSuite("rv32uc", rv32ucNames)(_)
|
||||
|
||||
val rv32umNames = LinkedHashSet("mul", "mulh", "mulhsu", "mulhu", "div", "divu", "rem", "remu")
|
||||
val rv32um = new AssemblyTestSuite("rv32um", rv32umNames)(_)
|
||||
|
||||
val rv32uaNames = LinkedHashSet("lrsc", "amoadd_w", "amoand_w", "amoor_w", "amoxor_w", "amoswap_w", "amomax_w", "amomaxu_w", "amomin_w", "amominu_w")
|
||||
val rv32ua = new AssemblyTestSuite("rv32ua", rv32uaNames)(_)
|
||||
|
||||
val rv32siNames = LinkedHashSet("csr", "ma_fetch", "scall", "sbreak", "wfi", "dirty")
|
||||
val rv32si = new AssemblyTestSuite("rv32si", rv32siNames)(_)
|
||||
|
||||
val rv32miNames = LinkedHashSet("csr", "mcsr", "illegal", "ma_addr", "ma_fetch", "sbreak", "scall")
|
||||
val rv32mi = new AssemblyTestSuite("rv32mi", rv32miNames)(_)
|
||||
|
||||
val rv32u = List(rv32ui, rv32um)
|
||||
val rv32i = List(rv32ui, rv32si, rv32mi)
|
||||
val rv32pi = List(rv32ui, rv32mi)
|
||||
|
||||
val rv64uiNames = LinkedHashSet("addw", "addiw", "ld", "lwu", "sd", "slliw", "sllw", "sltiu", "sltu", "sraiw", "sraw", "srliw", "srlw", "subw")
|
||||
val rv64ui = new AssemblyTestSuite("rv64ui", rv32uiNames ++ rv64uiNames)(_)
|
||||
|
||||
val rv64umNames = LinkedHashSet("divuw", "divw", "mulw", "remuw", "remw")
|
||||
val rv64um = new AssemblyTestSuite("rv64um", rv32umNames ++ rv64umNames)(_)
|
||||
|
||||
val rv64uaNames = rv32uaNames.map(_.replaceAll("_w","_d"))
|
||||
val rv64ua = new AssemblyTestSuite("rv64ua", rv32uaNames ++ rv64uaNames)(_)
|
||||
|
||||
val rv64ucNames = rv32ucNames
|
||||
val rv64uc = new AssemblyTestSuite("rv64uc", rv64ucNames)(_)
|
||||
|
||||
val rv64ufNames = LinkedHashSet("ldst", "move", "fsgnj", "fcmp", "fcvt", "fcvt_w", "fclass", "fadd", "fdiv", "fmin", "fmadd")
|
||||
val rv64uf = new AssemblyTestSuite("rv64uf", rv64ufNames)(_)
|
||||
val rv64ufNoDiv = new AssemblyTestSuite("rv64uf", rv64ufNames - "fdiv")(_)
|
||||
|
||||
val rv64udNames = rv64ufNames + "structural"
|
||||
val rv64ud = new AssemblyTestSuite("rv64ud", rv64udNames)(_)
|
||||
val rv64udNoDiv = new AssemblyTestSuite("rv64ud", rv64udNames - "fdiv")(_)
|
||||
|
||||
val rv64siNames = rv32siNames
|
||||
val rv64si = new AssemblyTestSuite("rv64si", rv64siNames)(_)
|
||||
|
||||
val rv64miNames = rv32miNames + "breakpoint"
|
||||
val rv64mi = new AssemblyTestSuite("rv64mi", rv64miNames)(_)
|
||||
|
||||
val groundtestNames = LinkedHashSet("simple")
|
||||
val groundtest64 = new AssemblyTestSuite("rv64ui", groundtestNames)(_)
|
||||
val groundtest32 = new AssemblyTestSuite("rv32ui", groundtestNames)(_)
|
||||
|
||||
// TODO: "rv64ui-pm-lrsc", "rv64mi-pm-ipi",
|
||||
|
||||
val rv64u = List(rv64ui, rv64um)
|
||||
val rv64i = List(rv64ui, rv64si, rv64mi)
|
||||
val rv64pi = List(rv64ui, rv64mi)
|
||||
|
||||
val benchmarks = new BenchmarkTestSuite("rvi", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet(
|
||||
"median", "multiply", "qsort", "towers", "vvadd", "dhrystone", "mt-matmul"))
|
||||
|
||||
val rv32udBenchmarks = new BenchmarkTestSuite("rvd", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet(
|
||||
"mm", "spmv", "mt-vvadd"))
|
||||
|
||||
val emptyBmarks = new BenchmarkTestSuite("empty",
|
||||
"$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet.empty)
|
||||
|
||||
val mtBmarks = new BenchmarkTestSuite("mt", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/mt",
|
||||
LinkedHashSet(((0 to 4).map("vvadd"+_) ++
|
||||
List("ad","ae","af","ag","ai","ak","al","am","an","ap","aq","ar","at","av","ay","az",
|
||||
"bb","bc","bf","bh","bj","bk","bm","bo","br","bs","ce","cf","cg","ci","ck","cl",
|
||||
"cm","cs","cv","cy","dc","df","dm","do","dr","ds","du","dv").map(_+"_matmul")): _*))
|
||||
}
|
||||
22
src/main/scala/coreplex/UnitTest.scala
Normal file
22
src/main/scala/coreplex/UnitTest.scala
Normal file
@ -0,0 +1,22 @@
|
||||
package coreplex
|
||||
|
||||
import Chisel._
|
||||
import junctions.unittests.UnitTestSuite
|
||||
import rocket.Tile
|
||||
import uncore.tilelink.TLId
|
||||
import cde.Parameters
|
||||
|
||||
class UnitTestCoreplex(topParams: Parameters) extends Coreplex()(topParams) {
|
||||
require(!exportMMIO)
|
||||
require(nExtClients == 0)
|
||||
require(nMemChannels == 0)
|
||||
|
||||
io.debug.req.ready := Bool(false)
|
||||
io.debug.resp.valid := Bool(false)
|
||||
|
||||
val l1params = p.alterPartial({ case TLId => "L1toL2" })
|
||||
val tests = Module(new UnitTestSuite()(l1params))
|
||||
|
||||
override def hasSuccessFlag = true
|
||||
io.success.get := tests.io.finished
|
||||
}
|
||||
Reference in New Issue
Block a user