From 7b0167b92e813525981d9177d4420e8b4f1c3888 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Fri, 25 Sep 2015 12:13:22 -0700
Subject: [PATCH] make sure SCR and PCR data width matches xLen

---
 src/main/scala/Configs.scala    |  1 +
 src/main/scala/RocketChip.scala | 10 ++++++----
 uncore                          |  2 +-
 3 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index 1ae3c666..98e853c4 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -31,6 +31,7 @@ class DefaultConfig extends ChiselConfig (
       //HTIF Parameters
       case HTIFWidth => Dump("HTIF_WIDTH", 16)
       case HTIFNSCR => 64
+      case HTIFSCRDataBits => site(XLen)
       case HTIFOffsetBits => site(CacheBlockOffsetBits)
       case HTIFNCores => site(NTiles)
       //Memory Parameters
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index ffe547a1..1bd91885 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -41,6 +41,8 @@ trait TopLevelParameters extends UsesParameters {
   val mifAddrBits = params(MIFAddrBits)
   val mifDataBeats = params(MIFDataBeats)
   val scrAddrBits = log2Up(params(HTIFNSCR))
+  val pcrAddrBits = 12
+  val xLen = params(XLen)
   require(lsb + log2Up(nBanks) < mifAddrBits)
 }
 
@@ -190,8 +192,8 @@ class OuterMemorySystem extends Module with TopLevelParameters {
     val mem = Vec(new NASTIIO, nMemChannels)
     val mem_backup = new MemSerializedIO(htifW)
     val mem_backup_en = Bool(INPUT)
-    val pcr = Vec(new SMIIO(64, 12), nTiles)
-    val scr = new SMIIO(64, scrAddrBits)
+    val pcr = Vec(new SMIIO(xLen, pcrAddrBits), nTiles)
+    val scr = new SMIIO(xLen, scrAddrBits)
     val mmio = new NASTIIO
   }
 
@@ -244,12 +246,12 @@ class OuterMemorySystem extends Module with TopLevelParameters {
   for (i <- 0 until nTiles) {
     val csrName = s"conf:csr$i"
     val csrPort = addrMap(csrName).port
-    val conv = Module(new SMIIONASTIIOConverter(64, 12))
+    val conv = Module(new SMIIONASTIIOConverter(xLen, pcrAddrBits))
     conv.io.nasti <> interconnect.io.slaves(csrPort)
     io.pcr(i) <> conv.io.smi
   }
 
-  val conv = Module(new SMIIONASTIIOConverter(64, scrAddrBits))
+  val conv = Module(new SMIIONASTIIOConverter(xLen, scrAddrBits))
   conv.io.nasti <> interconnect.io.slaves(addrMap("conf:scr").port)
   io.scr <> conv.io.smi
 
diff --git a/uncore b/uncore
index b6bb4e42..82805188 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit b6bb4e42127d1ed42b55ec8b859a4e074b347d47
+Subproject commit 828051888358284c1c6dfd6d91f4468b2a603579