add multiclock support to Coreplex
This commit is contained in:
Yunsup Lee
parent
8e63f4a1a5
commit
7afd630d3e
167
src/main/scala/coreplex/BaseCoreplex.scala
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167
src/main/scala/coreplex/BaseCoreplex.scala
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@ -0,0 +1,167 @@
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package coreplex
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import Chisel._
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import cde.{Parameters, Field}
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import junctions._
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import uncore.tilelink._
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import uncore.tilelink2._
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import uncore.coherence._
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import uncore.agents._
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import uncore.devices._
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import uncore.util._
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import uncore.converters._
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import rocket._
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import rocket.Util._
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/** Number of memory channels */
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case object NMemoryChannels extends Field[Int]
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/** Number of banks per memory channel */
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case object NBanksPerMemoryChannel extends Field[Int]
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/** Least significant bit of address used for bank partitioning */
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case object BankIdLSB extends Field[Int]
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/** Function for building some kind of coherence manager agent */
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case object BuildL2CoherenceManager extends Field[(Int, Parameters) => CoherenceAgent]
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/** Function for building some kind of tile connected to a reset signal */
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case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
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/** The file to read the BootROM contents from */
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case object BootROMFile extends Field[String]
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trait HasCoreplexParameters {
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implicit val p: Parameters
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lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
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lazy val lsb = p(BankIdLSB)
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lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
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lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" })
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lazy val outermostMMIOParams = p.alterPartial({ case TLId => "MMIO_Outermost" })
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lazy val globalAddrMap = p(rocketchip.GlobalAddrMap)
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}
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case class CoreplexConfig(
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nTiles: Int,
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nExtInterrupts: Int,
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nSlaves: Int,
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nMemChannels: Int,
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hasSupervisor: Boolean,
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hasExtMMIOPort: Boolean)
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{
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val plicKey = PLICConfig(nTiles, hasSupervisor, nExtInterrupts, 0)
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}
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abstract class BaseCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends LazyModule
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abstract class BaseCoreplexBundle(val c: CoreplexConfig)(implicit val p: Parameters) extends Bundle with HasCoreplexParameters {
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val master = new Bundle {
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val mem = Vec(c.nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))
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val mmio = c.hasExtMMIOPort.option(new ClientUncachedTileLinkIO()(outermostMMIOParams))
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}
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val slave = Vec(c.nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip
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val interrupts = Vec(c.nExtInterrupts, Bool()).asInput
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val debug = new DebugBusIO()(p).flip
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val clint = Vec(c.nTiles, new CoreplexLocalInterrupts).asInput
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val success = Bool(OUTPUT)
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val resetVector = UInt(INPUT, p(XLen))
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}
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abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
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c: CoreplexConfig, l: L, b: => B)(implicit val p: Parameters) extends LazyModuleImp(l) with HasCoreplexParameters {
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val outer: L = l
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val io: B = b
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// Coreplex doesn't know when to stop running
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io.success := Bool(false)
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// Build a set of Tiles
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val tiles = p(BuildTiles) map { _(reset, p) }
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val uncoreTileIOs = (tiles zipWithIndex) map { case (tile, i) => Wire(tile.io) }
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val nCachedPorts = tiles.map(tile => tile.io.cached.size).reduce(_ + _)
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val nUncachedPorts = tiles.map(tile => tile.io.uncached.size).reduce(_ + _)
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val nBanks = c.nMemChannels * nBanksPerMemChannel
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// Build an uncore backing the Tiles
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buildUncore(p.alterPartial({
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case HastiId => "TL"
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case TLId => "L1toL2"
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case NCachedTileLinkPorts => nCachedPorts
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case NUncachedTileLinkPorts => nUncachedPorts
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}))
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def buildUncore(implicit p: Parameters) = {
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// Create a simple L1toL2 NoC between the tiles and the banks of outer memory
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// Cached ports are first in client list, making sharerToClientId just an indentity function
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// addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
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def sharerToClientId(sharerId: UInt) = sharerId
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def addrToBank(addr: UInt): UInt = if (nBanks == 0) UInt(0) else {
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val isMemory = globalAddrMap.isInRegion("mem", addr << log2Up(p(CacheBlockBytes)))
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Mux(isMemory, addr.extract(lsb + log2Ceil(nBanks) - 1, lsb), UInt(nBanks))
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}
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val l1tol2net = Module(new PortedTileLinkCrossbar(addrToBank, sharerToClientId))
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// Create point(s) of coherence serialization
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val managerEndpoints = List.tabulate(nBanks){id => p(BuildL2CoherenceManager)(id, p)}
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managerEndpoints.flatMap(_.incoherent).foreach(_ := Bool(false))
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val mmioManager = Module(new MMIOTileLinkManager()(p.alterPartial({
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case TLId => "L1toL2"
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMMIO"
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})))
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// Wire the tiles to the TileLink client ports of the L1toL2 network,
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// and coherence manager(s) to the other side
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l1tol2net.io.clients_cached <> uncoreTileIOs.map(_.cached).flatten
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l1tol2net.io.clients_uncached <> uncoreTileIOs.map(_.uncached).flatten ++ io.slave
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l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner
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// Create a converter between TileLinkIO and MemIO for each channel
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val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, c.nMemChannels)(outermostParams))
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val outerTLParams = p.alterPartial({ case TLId => "L2toMC" })
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val backendBuffering = TileLinkDepths(0,0,0,0,0)
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for ((bank, icPort) <- managerEndpoints zip mem_ic.io.in) {
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val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
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unwrap.io.in <> TileLinkEnqueuer(bank.outerTL, backendBuffering)(outerTLParams)
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TileLinkWidthAdapter(icPort, unwrap.io.out)
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}
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io.master.mem <> mem_ic.io.out
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buildMMIONetwork(TileLinkEnqueuer(mmioManager.io.outer, 1))(
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p.alterPartial({case TLId => "L2toMMIO"}))
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}
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def buildMMIONetwork(mmio: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
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val ioAddrMap = globalAddrMap.subMap("io")
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val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap))
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mmioNetwork.io.in.head <> mmio
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val plic = Module(new PLIC(c.plicKey))
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plic.io.tl <> mmioNetwork.port("int:plic")
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for (i <- 0 until io.interrupts.size) {
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val gateway = Module(new LevelGateway)
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gateway.io.interrupt := io.interrupts(i)
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plic.io.devices(i) <> gateway.io.plic
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}
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val debugModule = Module(new DebugModule)
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debugModule.io.tl <> mmioNetwork.port("int:debug")
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debugModule.io.db <> io.debug
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// connect coreplex-internal interrupts to tiles
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for ((tile, i) <- (uncoreTileIOs zipWithIndex)) {
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tile.interrupts := io.clint(i)
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tile.interrupts.meip := plic.io.harts(plic.cfg.context(i, 'M'))
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tile.interrupts.seip.foreach(_ := plic.io.harts(plic.cfg.context(i, 'S')))
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tile.interrupts.debug := debugModule.io.debugInterrupts(i)
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tile.hartid := i
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tile.resetVector := io.resetVector
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}
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val tileSlavePorts = (0 until c.nTiles) map (i => s"int:dmem$i") filter (ioAddrMap contains _)
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for ((t, m) <- (uncoreTileIOs.map(_.slave).flatten) zip (tileSlavePorts map (mmioNetwork port _)))
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t <> m
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io.master.mmio.foreach { _ <> mmioNetwork.port("ext") }
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}
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}
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@ -4,165 +4,81 @@ import Chisel._
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import cde.{Parameters, Field}
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import junctions._
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import uncore.tilelink._
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import uncore.coherence._
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import uncore.agents._
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import uncore.devices._
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import uncore.util._
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import uncore.converters._
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import rocket._
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import rocket.Util._
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/** Number of memory channels */
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case object NMemoryChannels extends Field[Int]
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/** Number of banks per memory channel */
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case object NBanksPerMemoryChannel extends Field[Int]
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/** Least significant bit of address used for bank partitioning */
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case object BankIdLSB extends Field[Int]
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/** Function for building some kind of coherence manager agent */
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case object BuildL2CoherenceManager extends Field[(Int, Parameters) => CoherenceAgent]
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/** Function for building some kind of tile connected to a reset signal */
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case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
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/** The file to read the BootROM contents from */
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case object BootROMFile extends Field[String]
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trait DirectConnection {
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val tiles: Seq[Tile]
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val uncoreTileIOs: Seq[TileIO]
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trait HasCoreplexParameters {
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implicit val p: Parameters
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lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
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lazy val lsb = p(BankIdLSB)
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lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
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lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" })
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lazy val outermostMMIOParams = p.alterPartial({ case TLId => "MMIO_Outermost" })
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lazy val globalAddrMap = p(rocketchip.GlobalAddrMap)
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}
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val tlBuffering = TileLinkDepths(1,1,2,2,0)
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val ultBuffering = UncachedTileLinkDepths(1,2)
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case class CoreplexConfig(
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nTiles: Int,
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nExtInterrupts: Int,
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nSlaves: Int,
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nMemChannels: Int,
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hasSupervisor: Boolean,
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hasExtMMIOPort: Boolean)
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{
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val plicKey = PLICConfig(nTiles, hasSupervisor, nExtInterrupts, 0)
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}
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(tiles zip uncoreTileIOs) foreach { case (tile, uncore) =>
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(uncore.cached zip tile.io.cached) foreach { case (u, t) => u <> TileLinkEnqueuer(t, tlBuffering)(t.p) }
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(uncore.uncached zip tile.io.uncached) foreach { case (u, t) => u <> TileLinkEnqueuer(t, ultBuffering)(t.p) }
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tile.io.slave.foreach { _ <> TileLinkEnqueuer(uncore.slave.get, 1)(uncore.slave.get.p) }
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abstract class Coreplex(implicit val p: Parameters, implicit val c: CoreplexConfig) extends Module
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with HasCoreplexParameters {
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class CoreplexIO(implicit val p: Parameters, implicit val c: CoreplexConfig) extends Bundle {
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val master = new Bundle {
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val mem = Vec(c.nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))
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val mmio = c.hasExtMMIOPort.option(new ClientUncachedTileLinkIO()(outermostMMIOParams))
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}
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val slave = Vec(c.nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip
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val interrupts = Vec(c.nExtInterrupts, Bool()).asInput
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val debug = new DebugBusIO()(p).flip
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val clint = Vec(c.nTiles, new CoreplexLocalInterrupts).asInput
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val success = Bool(OUTPUT)
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val resetVector = UInt(INPUT, p(XLen))
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}
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tile.io.interrupts <> uncore.interrupts
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val io = new CoreplexIO
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}
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class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp, tc) {
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// Coreplex doesn't know when to stop running
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io.success := Bool(false)
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// Build a set of Tiles
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val tileResets = Wire(Vec(tc.nTiles, Bool()))
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val tileList = p(BuildTiles).zip(tileResets).map {
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case (tile, rst) => tile(rst, p)
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}
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val nCachedPorts = tileList.map(tile => tile.io.cached.size).reduce(_ + _)
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val nUncachedPorts = tileList.map(tile => tile.io.uncached.size).reduce(_ + _)
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val nBanks = tc.nMemChannels * nBanksPerMemChannel
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// Build an uncore backing the Tiles
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buildUncore(p.alterPartial({
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case HastiId => "TL"
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case TLId => "L1toL2"
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case NCachedTileLinkPorts => nCachedPorts
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case NUncachedTileLinkPorts => nUncachedPorts
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}))
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def buildUncore(implicit p: Parameters) = {
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// Create a simple L1toL2 NoC between the tiles and the banks of outer memory
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// Cached ports are first in client list, making sharerToClientId just an indentity function
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// addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
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def sharerToClientId(sharerId: UInt) = sharerId
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def addrToBank(addr: UInt): UInt = if (nBanks == 0) UInt(0) else {
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val isMemory = globalAddrMap.isInRegion("mem", addr << log2Up(p(CacheBlockBytes)))
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Mux(isMemory, addr.extract(lsb + log2Ceil(nBanks) - 1, lsb), UInt(nBanks))
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}
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val preBuffering = TileLinkDepths(1,1,2,2,0)
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val l1tol2net = Module(new PortedTileLinkCrossbar(addrToBank, sharerToClientId, preBuffering))
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// Create point(s) of coherence serialization
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val managerEndpoints = List.tabulate(nBanks){id => p(BuildL2CoherenceManager)(id, p)}
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managerEndpoints.flatMap(_.incoherent).foreach(_ := Bool(false))
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val mmioManager = Module(new MMIOTileLinkManager()(p.alterPartial({
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case TLId => "L1toL2"
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMMIO"
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})))
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// Wire the tiles to the TileLink client ports of the L1toL2 network,
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// and coherence manager(s) to the other side
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l1tol2net.io.clients_cached <> tileList.map(_.io.cached).flatten
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l1tol2net.io.clients_uncached <> tileList.map(_.io.uncached).flatten ++ io.slave
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l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner
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// Create a converter between TileLinkIO and MemIO for each channel
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val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, tc.nMemChannels)(outermostParams))
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val outerTLParams = p.alterPartial({ case TLId => "L2toMC" })
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val backendBuffering = TileLinkDepths(0,0,0,0,0)
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for ((bank, icPort) <- managerEndpoints zip mem_ic.io.in) {
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val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
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unwrap.io.in <> TileLinkEnqueuer(bank.outerTL, backendBuffering)(outerTLParams)
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TileLinkWidthAdapter(icPort, unwrap.io.out)
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}
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io.master.mem <> mem_ic.io.out
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buildMMIONetwork(TileLinkEnqueuer(mmioManager.io.outer, 1))(
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p.alterPartial({case TLId => "L2toMMIO"}))
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}
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def buildMMIONetwork(mmio: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
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val ioAddrMap = globalAddrMap.subMap("io")
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val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap))
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mmioNetwork.io.in.head <> mmio
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val plic = Module(new PLIC(c.plicKey))
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plic.io.tl <> mmioNetwork.port("int:plic")
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for (i <- 0 until io.interrupts.size) {
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val gateway = Module(new LevelGateway)
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gateway.io.interrupt := io.interrupts(i)
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plic.io.devices(i) <> gateway.io.plic
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}
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val debugModule = Module(new DebugModule)
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debugModule.io.tl <> mmioNetwork.port("int:debug")
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debugModule.io.db <> io.debug
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// connect coreplex-internal interrupts to tiles
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for (((tile, tileReset), i) <- (tileList zip tileResets) zipWithIndex) {
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tileReset := reset // TODO should tiles be reset separately from coreplex?
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tile.io.interrupts := io.clint(i)
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tile.io.interrupts.meip := plic.io.harts(plic.cfg.context(i, 'M'))
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tile.io.interrupts.seip.foreach(_ := plic.io.harts(plic.cfg.context(i, 'S')))
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tile.io.interrupts.debug := debugModule.io.debugInterrupts(i)
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tile.io.hartid := i
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tile.io.resetVector := io.resetVector
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}
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val tileSlavePorts = (0 until tc.nTiles) map (i => s"int:dmem$i") filter (ioAddrMap contains _)
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for ((t, m) <- (tileList.map(_.io.slave).flatten) zip (tileSlavePorts map (mmioNetwork port _)))
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t <> TileLinkEnqueuer(m, 1)
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io.master.mmio.foreach { _ <> mmioNetwork.port("ext") }
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tile.io.hartid := uncore.hartid
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tile.io.resetVector := uncore.resetVector
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}
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}
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class DefaultCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplex(c)(p) {
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override lazy val module = Module(new DefaultCoreplexModule(c, this, new DefaultCoreplexBundle(c)(p))(p))
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}
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class DefaultCoreplexBundle(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplexBundle(c)(p)
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class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle](
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c: CoreplexConfig, l: L, b: => B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p)
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with DirectConnection
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/////
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trait TileClockResetBundle {
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val c: CoreplexConfig
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val trcs = Vec(c.nTiles, new Bundle {
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val clock = Clock(INPUT)
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val reset = Bool(INPUT)
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})
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}
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trait AsyncConnection {
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val io: TileClockResetBundle
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val tiles: Seq[Tile]
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val uncoreTileIOs: Seq[TileIO]
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(tiles, uncoreTileIOs, io.trcs).zipped foreach { case (tile, uncore, trc) =>
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tile.clock := trc.clock
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tile.reset := trc.reset
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(uncore.cached zip tile.io.cached) foreach { case (u, t) => u <> AsyncTileLinkFrom(trc.clock, trc.reset, t) }
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(uncore.uncached zip tile.io.uncached) foreach { case (u, t) => u <> AsyncUTileLinkFrom(trc.clock, trc.reset, t) }
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tile.io.slave.foreach { _ <> AsyncUTileLinkTo(trc.clock, trc.reset, uncore.slave.get)}
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val ti = tile.io.interrupts
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val ui = uncore.interrupts
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ti.debug := LevelSyncTo(trc.clock, ui.debug)
|
||||
ti.mtip := LevelSyncTo(trc.clock, ui.mtip)
|
||||
ti.msip := LevelSyncTo(trc.clock, ui.msip)
|
||||
ti.meip := LevelSyncTo(trc.clock, ui.meip)
|
||||
ti.seip.foreach { _ := LevelSyncTo(trc.clock, ui.seip.get) }
|
||||
|
||||
tile.io.hartid := uncore.hartid
|
||||
tile.io.resetVector := uncore.resetVector
|
||||
}
|
||||
}
|
||||
|
||||
class MultiClockCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplex(c)(p) {
|
||||
override lazy val module = Module(new MultiClockCoreplexModule(c, this, new MultiClockCoreplexBundle(c)(p))(p))
|
||||
}
|
||||
|
||||
class MultiClockCoreplexBundle(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplexBundle(c)(p)
|
||||
with TileClockResetBundle
|
||||
|
||||
class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle](
|
||||
c: CoreplexConfig, l: L, b: => B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p)
|
||||
with AsyncConnection
|
||||
|
||||
@ -83,7 +83,7 @@ class PCIeMockupTestConfig extends Config(
|
||||
class WithGroundTest extends Config(
|
||||
(pname, site, here) => pname match {
|
||||
case BuildCoreplex =>
|
||||
(p: Parameters, c: CoreplexConfig) => Module(new GroundTestCoreplex(p, c))
|
||||
(c: CoreplexConfig, p: Parameters) => uncore.tilelink2.LazyModule(new GroundTestCoreplex(c)(p)).module
|
||||
case TLKey("L1toL2") => {
|
||||
val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
|
||||
TileLinkParameters(
|
||||
|
||||
@ -2,8 +2,15 @@ package groundtest
|
||||
|
||||
import Chisel._
|
||||
import cde.{Parameters}
|
||||
import coreplex.{CoreplexConfig, DefaultCoreplex}
|
||||
import coreplex._
|
||||
|
||||
class GroundTestCoreplex(tp: Parameters, tc: CoreplexConfig) extends DefaultCoreplex(tp, tc) {
|
||||
io.success := tileList.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
|
||||
class GroundTestCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplex(c)(p) {
|
||||
override lazy val module = Module(new GroundTestCoreplexModule(c, this, new GroundTestCoreplexBundle(c)(p))(p))
|
||||
}
|
||||
|
||||
class GroundTestCoreplexBundle(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplexBundle(c)(p)
|
||||
|
||||
class GroundTestCoreplexModule[+L <: GroundTestCoreplex, +B <: GroundTestCoreplexBundle](
|
||||
c: CoreplexConfig, l: L, b: => B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p) with DirectConnection {
|
||||
io.success := tiles.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
|
||||
}
|
||||
|
||||
@ -101,7 +101,7 @@ class GroundTestTile(resetSignal: Bool)
|
||||
extends Tile(resetSignal = resetSignal)(p)
|
||||
with HasGroundTestParameters {
|
||||
|
||||
override val io = new TileIO {
|
||||
override val io = new TileIO(bc) {
|
||||
val success = Bool(OUTPUT)
|
||||
}
|
||||
|
||||
|
||||
@ -85,3 +85,50 @@ object AsyncIrrevocableFrom
|
||||
PostQueueIrrevocablize(AsyncDecoupledFrom(from_clock, from_reset, from_source, depth, sync))
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* This helper object synchronizes a level-sensitive signal from one
|
||||
* clock domain to another.
|
||||
*/
|
||||
object LevelSyncCrossing {
|
||||
class SynchronizerBackend(sync: Int, _clock: Clock) extends Module(Some(_clock)) {
|
||||
val io = new Bundle {
|
||||
val in = Bool(INPUT)
|
||||
val out = Bool(OUTPUT)
|
||||
}
|
||||
|
||||
io.out := ShiftRegister(io.in, sync)
|
||||
}
|
||||
|
||||
class SynchronizerFrontend(_clock: Clock) extends Module(Some(_clock)) {
|
||||
val io = new Bundle {
|
||||
val in = Bool(INPUT)
|
||||
val out = Bool(OUTPUT)
|
||||
}
|
||||
|
||||
io.out := RegNext(io.in)
|
||||
}
|
||||
|
||||
def apply(from_clock: Clock, to_clock: Clock, in: Bool, sync: Int = 2): Bool = {
|
||||
val front = Module(new SynchronizerFrontend(from_clock))
|
||||
val back = Module(new SynchronizerBackend(sync, to_clock))
|
||||
|
||||
front.io.in := in
|
||||
back.io.in := front.io.out
|
||||
back.io.out
|
||||
}
|
||||
}
|
||||
|
||||
object LevelSyncTo {
|
||||
def apply(to_clock: Clock, in: Bool, sync: Int = 2): Bool = {
|
||||
val scope = AsyncScope()
|
||||
LevelSyncCrossing(scope.clock, to_clock, in, sync)
|
||||
}
|
||||
}
|
||||
|
||||
object LevelSyncFrom {
|
||||
def apply(from_clock: Clock, in: Bool, sync: Int = 2): Bool = {
|
||||
val scope = AsyncScope()
|
||||
LevelSyncCrossing(from_clock, scope.clock, in, sync)
|
||||
}
|
||||
}
|
||||
|
||||
@ -22,22 +22,35 @@ case class RoccParameters(
|
||||
nPTWPorts : Int = 0,
|
||||
useFPU: Boolean = false)
|
||||
|
||||
case class TileBundleConfig(
|
||||
nCachedTileLinkPorts: Int,
|
||||
nUncachedTileLinkPorts: Int,
|
||||
xLen: Int,
|
||||
hasSlavePort: Boolean)
|
||||
|
||||
class TileIO(c: TileBundleConfig)(implicit p: Parameters) extends Bundle {
|
||||
val cached = Vec(c.nCachedTileLinkPorts, new ClientTileLinkIO)
|
||||
val uncached = Vec(c.nUncachedTileLinkPorts, new ClientUncachedTileLinkIO)
|
||||
val hartid = UInt(INPUT, c.xLen)
|
||||
val interrupts = new TileInterrupts().asInput
|
||||
val slave = c.hasSlavePort.option(new ClientUncachedTileLinkIO().flip)
|
||||
val resetVector = UInt(INPUT, c.xLen)
|
||||
|
||||
override def cloneType = new TileIO(c).asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
abstract class Tile(clockSignal: Clock = null, resetSignal: Bool = null)
|
||||
(implicit p: Parameters) extends Module(Option(clockSignal), Option(resetSignal)) {
|
||||
val nCachedTileLinkPorts = p(NCachedTileLinkPorts)
|
||||
val nUncachedTileLinkPorts = p(NUncachedTileLinkPorts)
|
||||
val dcacheParams = p.alterPartial({ case CacheName => "L1D" })
|
||||
val bc = TileBundleConfig(
|
||||
nCachedTileLinkPorts = nCachedTileLinkPorts,
|
||||
nUncachedTileLinkPorts = nUncachedTileLinkPorts,
|
||||
xLen = p(XLen),
|
||||
hasSlavePort = p(DataScratchpadSize) > 0)
|
||||
|
||||
class TileIO extends Bundle {
|
||||
val cached = Vec(nCachedTileLinkPorts, new ClientTileLinkIO)
|
||||
val uncached = Vec(nUncachedTileLinkPorts, new ClientUncachedTileLinkIO)
|
||||
val hartid = UInt(INPUT, p(XLen))
|
||||
val interrupts = new TileInterrupts().asInput
|
||||
val slave = (p(DataScratchpadSize) > 0).option(new ClientUncachedTileLinkIO().flip)
|
||||
val resetVector = UInt(INPUT, p(XLen))
|
||||
}
|
||||
|
||||
val io = new TileIO
|
||||
val io = new TileIO(bc)
|
||||
}
|
||||
|
||||
class RocketTile(clockSignal: Clock = null, resetSignal: Bool = null)
|
||||
|
||||
@ -18,7 +18,7 @@ case object GlobalAddrMap extends Field[AddrMap]
|
||||
case object ConfigString extends Field[String]
|
||||
case object NCoreplexExtClients extends Field[Int]
|
||||
/** Function for building Coreplex */
|
||||
case object BuildCoreplex extends Field[(Parameters, CoreplexConfig) => Coreplex]
|
||||
case object BuildCoreplex extends Field[(CoreplexConfig, Parameters) => BaseCoreplexModule[BaseCoreplex, BaseCoreplexBundle]]
|
||||
|
||||
/** Base Top with no Periphery */
|
||||
abstract class BaseTop(q: Parameters) extends LazyModule {
|
||||
@ -53,20 +53,22 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
|
||||
peripheryBus.node := TLBuffer(TLWidthWidget(TLHintHandler(legacy.node), legacy.tlDataBytes))
|
||||
}
|
||||
|
||||
class BaseTopBundle(val p: Parameters, val c: Coreplex) extends ParameterizedBundle()(p) {
|
||||
abstract class BaseTopBundle(val p: Parameters) extends Bundle {
|
||||
val success = Bool(OUTPUT)
|
||||
}
|
||||
|
||||
abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L, b: Coreplex => B) extends LazyModuleImp(l) {
|
||||
abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](
|
||||
val p: Parameters, l: L, b: => B) extends LazyModuleImp(l) {
|
||||
val outer: L = l
|
||||
val io: B = b
|
||||
|
||||
val coreplex = p(BuildCoreplex)(p, outer.c)
|
||||
val io: B = b(coreplex)
|
||||
val coreplex = p(BuildCoreplex)(outer.c, p)
|
||||
val coreplexIO = coreplex.io
|
||||
|
||||
val mmioNetwork =
|
||||
Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).subMap("io:ext"))(
|
||||
p.alterPartial({ case TLId => "L2toMMIO" })))
|
||||
mmioNetwork.io.in.head <> coreplex.io.master.mmio.get
|
||||
mmioNetwork.io.in.head <> coreplexIO.master.mmio.get
|
||||
outer.legacy.module.io.legacy <> mmioNetwork.port("TL2")
|
||||
|
||||
println("Generated Address Map")
|
||||
@ -86,5 +88,5 @@ abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Paramete
|
||||
println(p(ConfigString))
|
||||
ConfigStringOutput.contents = Some(p(ConfigString))
|
||||
|
||||
io.success := coreplex.io.success
|
||||
io.success := coreplexIO.success
|
||||
}
|
||||
|
||||
@ -40,7 +40,7 @@ class BasePlatformConfig extends Config(
|
||||
idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
|
||||
}
|
||||
case BuildCoreplex =>
|
||||
(p: Parameters, c: CoreplexConfig) => Module(new DefaultCoreplex(p, c))
|
||||
(c: CoreplexConfig, p: Parameters) => uncore.tilelink2.LazyModule(new DefaultCoreplex(c)(p)).module
|
||||
case NExtTopInterrupts => 2
|
||||
// Note that PLIC asserts that this is > 0.
|
||||
case AsyncDebugBus => false
|
||||
|
||||
@ -4,33 +4,66 @@ package rocketchip
|
||||
|
||||
import Chisel._
|
||||
import cde.{Parameters, Field}
|
||||
import coreplex.Coreplex
|
||||
import junctions._
|
||||
import coreplex._
|
||||
import rocketchip._
|
||||
|
||||
/** Example Top with Periphery */
|
||||
class ExampleTop(q: Parameters) extends BaseTop(q)
|
||||
with PeripheryBootROM with PeripheryDebug with PeripheryExtInterrupts with PeripheryCoreplexLocalInterrupter
|
||||
with PeripheryMasterMem with PeripheryMasterMMIO with PeripherySlave {
|
||||
override lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p, _)))
|
||||
with PeripheryBootROM
|
||||
with PeripheryDebug
|
||||
with PeripheryExtInterrupts
|
||||
with PeripheryCoreplexLocalInterrupter
|
||||
with PeripheryMasterMem
|
||||
with PeripheryMasterMMIO
|
||||
with PeripherySlave {
|
||||
override lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p)))
|
||||
}
|
||||
|
||||
class ExampleTopBundle(p: Parameters, c: Coreplex) extends BaseTopBundle(p, c)
|
||||
with PeripheryBootROMBundle with PeripheryDebugBundle with PeripheryExtInterruptsBundle with PeripheryCoreplexLocalInterrupterBundle
|
||||
with PeripheryMasterMemBundle with PeripheryMasterMMIOBundle with PeripherySlaveBundle
|
||||
class ExampleTopBundle(p: Parameters) extends BaseTopBundle(p)
|
||||
with PeripheryBootROMBundle
|
||||
with PeripheryDebugBundle
|
||||
with PeripheryExtInterruptsBundle
|
||||
with PeripheryCoreplexLocalInterrupterBundle
|
||||
with PeripheryMasterMemBundle
|
||||
with PeripheryMasterMMIOBundle
|
||||
with PeripherySlaveBundle
|
||||
|
||||
class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: Coreplex => B) extends BaseTopModule(p, l, b)
|
||||
with PeripheryBootROMModule with PeripheryDebugModule with PeripheryExtInterruptsModule with PeripheryCoreplexLocalInterrupterModule
|
||||
with PeripheryMasterMemModule with PeripheryMasterMMIOModule with PeripherySlaveModule
|
||||
class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: => B) extends BaseTopModule(p, l, b)
|
||||
with PeripheryBootROMModule
|
||||
with PeripheryDebugModule
|
||||
with PeripheryExtInterruptsModule
|
||||
with PeripheryCoreplexLocalInterrupterModule
|
||||
with PeripheryMasterMemModule
|
||||
with PeripheryMasterMMIOModule
|
||||
with PeripherySlaveModule
|
||||
with HardwiredResetVector
|
||||
|
||||
/** Example Top with TestRAM */
|
||||
class ExampleTopWithTestRAM(q: Parameters) extends ExampleTop(q)
|
||||
with PeripheryTestRAM {
|
||||
override lazy val module = Module(new ExampleTopWithTestRAMModule(p, this, new ExampleTopWithTestRAMBundle(p, _)))
|
||||
override lazy val module = Module(new ExampleTopWithTestRAMModule(p, this, new ExampleTopWithTestRAMBundle(p)))
|
||||
}
|
||||
|
||||
class ExampleTopWithTestRAMBundle(p: Parameters, c: Coreplex) extends ExampleTopBundle(p, c)
|
||||
class ExampleTopWithTestRAMBundle(p: Parameters) extends ExampleTopBundle(p)
|
||||
with PeripheryTestRAMBundle
|
||||
|
||||
class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM, +B <: ExampleTopWithTestRAMBundle](p: Parameters, l: L, b: Coreplex => B) extends ExampleTopModule(p, l, b)
|
||||
class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM, +B <: ExampleTopWithTestRAMBundle](p: Parameters, l: L, b: => B) extends ExampleTopModule(p, l, b)
|
||||
with PeripheryTestRAMModule
|
||||
|
||||
/** Example Top with Multi Clock */
|
||||
class ExampleMultiClockTop(q: Parameters) extends ExampleTop(q)
|
||||
with PeripheryTestRAM {
|
||||
override lazy val module = Module(new ExampleMultiClockTopModule(p, this, new ExampleMultiClockTopBundle(p)))
|
||||
}
|
||||
|
||||
class ExampleMultiClockTopBundle(p: Parameters) extends ExampleTopBundle(p)
|
||||
|
||||
class ExampleMultiClockTopModule[+L <: ExampleMultiClockTop, +B <: ExampleMultiClockTopBundle](p: Parameters, l: L, b: => B) extends ExampleTopModule(p, l, b) {
|
||||
val multiClockCoreplexIO = coreplexIO.asInstanceOf[MultiClockCoreplexBundle]
|
||||
|
||||
multiClockCoreplexIO.trcs foreach { trc =>
|
||||
trc.clock := clock
|
||||
trc.reset := reset
|
||||
}
|
||||
}
|
||||
|
||||
@ -101,16 +101,16 @@ trait PeripheryDebugModule {
|
||||
implicit val p: Parameters
|
||||
val outer: PeripheryDebug
|
||||
val io: PeripheryDebugBundle
|
||||
val coreplex: Coreplex
|
||||
val coreplexIO: BaseCoreplexBundle
|
||||
|
||||
if (p(IncludeJtagDTM)) {
|
||||
// JtagDTMWithSync is a wrapper which
|
||||
// handles the synchronization as well.
|
||||
val dtm = Module (new JtagDTMWithSync()(p))
|
||||
dtm.io.jtag <> io.jtag.get
|
||||
coreplex.io.debug <> dtm.io.debug
|
||||
coreplexIO.debug <> dtm.io.debug
|
||||
} else {
|
||||
coreplex.io.debug <>
|
||||
coreplexIO.debug <>
|
||||
(if (p(AsyncDebugBus)) AsyncDebugBusFrom(io.debug_clk.get, io.debug_rst.get, io.debug.get)
|
||||
else io.debug.get)
|
||||
}
|
||||
@ -134,12 +134,12 @@ trait PeripheryExtInterruptsModule {
|
||||
implicit val p: Parameters
|
||||
val outer: PeripheryExtInterrupts
|
||||
val io: PeripheryExtInterruptsBundle
|
||||
val coreplex: Coreplex
|
||||
val coreplexIO: BaseCoreplexBundle
|
||||
|
||||
{
|
||||
val r = outer.pInterrupts.range("ext")
|
||||
((r._1 until r._2) zipWithIndex) foreach { case (c, i) =>
|
||||
coreplex.io.interrupts(c) := io.interrupts(i)
|
||||
coreplexIO.interrupts(c) := io.interrupts(i)
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -163,10 +163,10 @@ trait PeripheryMasterMemModule extends HasPeripheryParameters {
|
||||
implicit val p: Parameters
|
||||
val outer: PeripheryMasterMem
|
||||
val io: PeripheryMasterMemBundle
|
||||
val coreplex: Coreplex
|
||||
val coreplexIO: BaseCoreplexBundle
|
||||
|
||||
// Abuse the fact that zip takes the shorter of the two lists
|
||||
((io.mem_axi zip coreplex.io.master.mem) zipWithIndex) foreach { case ((axi, mem), idx) =>
|
||||
((io.mem_axi zip coreplexIO.master.mem) zipWithIndex) foreach { case ((axi, mem), idx) =>
|
||||
val axi_sync = PeripheryUtils.convertTLtoAXI(mem)(outermostParams)
|
||||
axi_sync.ar.bits.cache := CACHE_NORMAL_NOCACHE_BUF
|
||||
axi_sync.aw.bits.cache := CACHE_NORMAL_NOCACHE_BUF
|
||||
@ -176,11 +176,11 @@ trait PeripheryMasterMemModule extends HasPeripheryParameters {
|
||||
)
|
||||
}
|
||||
|
||||
(io.mem_ahb zip coreplex.io.master.mem) foreach { case (ahb, mem) =>
|
||||
(io.mem_ahb zip coreplexIO.master.mem) foreach { case (ahb, mem) =>
|
||||
ahb <> PeripheryUtils.convertTLtoAHB(mem, atomics = false)(outermostParams)
|
||||
}
|
||||
|
||||
(io.mem_tl zip coreplex.io.master.mem) foreach { case (tl, mem) =>
|
||||
(io.mem_tl zip coreplexIO.master.mem) foreach { case (tl, mem) =>
|
||||
tl <> TileLinkEnqueuer(mem, 2)(outermostParams)
|
||||
}
|
||||
}
|
||||
@ -258,7 +258,7 @@ trait PeripherySlaveModule extends HasPeripheryParameters {
|
||||
implicit val p: Parameters
|
||||
val outer: PeripherySlave
|
||||
val io: PeripherySlaveBundle
|
||||
val coreplex: Coreplex
|
||||
val coreplexIO: BaseCoreplexBundle
|
||||
|
||||
if (p(NExtBusAXIChannels) > 0) {
|
||||
val arb = Module(new NastiArbiter(p(NExtBusAXIChannels)))
|
||||
@ -273,7 +273,7 @@ trait PeripherySlaveModule extends HasPeripheryParameters {
|
||||
|
||||
val r = outer.pBusMasters.range("ext")
|
||||
require(r._2 - r._1 == 1, "RangeManager should return 1 slot")
|
||||
coreplex.io.slave(r._1) <> conv.io.tl
|
||||
coreplexIO.slave(r._1) <> conv.io.tl
|
||||
}
|
||||
}
|
||||
|
||||
@ -299,10 +299,10 @@ trait PeripheryCoreplexLocalInterrupterModule extends HasPeripheryParameters {
|
||||
implicit val p: Parameters
|
||||
val outer: PeripheryCoreplexLocalInterrupter
|
||||
val io: PeripheryCoreplexLocalInterrupterBundle
|
||||
val coreplex: Coreplex
|
||||
val coreplexIO: BaseCoreplexBundle
|
||||
|
||||
outer.clint.module.io.rtcTick := Counter(p(RTCPeriod)).inc()
|
||||
coreplex.io.clint <> outer.clint.module.io.tiles
|
||||
coreplexIO.clint <> outer.clint.module.io.tiles
|
||||
}
|
||||
|
||||
/////
|
||||
@ -371,6 +371,6 @@ trait PeripheryTestBusMasterModule {
|
||||
/////
|
||||
|
||||
trait HardwiredResetVector {
|
||||
val coreplex: Coreplex
|
||||
coreplex.io.resetVector := UInt(0x1000) // boot ROM
|
||||
val coreplexIO: BaseCoreplexBundle
|
||||
coreplexIO.resetVector := UInt(0x1000) // boot ROM
|
||||
}
|
||||
|
||||
53
src/main/scala/uncore/tilelink/Crossing.scala
Normal file
53
src/main/scala/uncore/tilelink/Crossing.scala
Normal file
@ -0,0 +1,53 @@
|
||||
package uncore.tilelink
|
||||
|
||||
import Chisel._
|
||||
import junctions._
|
||||
|
||||
object AsyncClientUncachedTileLinkCrossing {
|
||||
def apply(from_clock: Clock, from_reset: Bool, from_source: ClientUncachedTileLinkIO, to_clock: Clock, to_reset: Bool, depth: Int = 8, sync: Int = 3): ClientUncachedTileLinkIO = {
|
||||
val to_sink = Wire(new ClientUncachedTileLinkIO()(from_source.p))
|
||||
to_sink.acquire <> AsyncDecoupledCrossing(from_clock, from_reset, from_source.acquire, to_clock, to_reset, depth, sync)
|
||||
from_source.grant <> AsyncDecoupledCrossing(to_clock, to_reset, to_sink.grant, from_clock, from_reset, depth, sync)
|
||||
to_sink
|
||||
}
|
||||
}
|
||||
|
||||
object AsyncClientTileLinkCrossing {
|
||||
def apply(from_clock: Clock, from_reset: Bool, from_source: ClientTileLinkIO, to_clock: Clock, to_reset: Bool, depth: Int = 8, sync: Int = 3): ClientTileLinkIO = {
|
||||
val to_sink = Wire(new ClientTileLinkIO()(from_source.p))
|
||||
to_sink.acquire <> AsyncDecoupledCrossing(from_clock, from_reset, from_source.acquire, to_clock, to_reset, depth, sync)
|
||||
to_sink.release <> AsyncDecoupledCrossing(from_clock, from_reset, from_source.release, to_clock, to_reset, depth, sync)
|
||||
to_sink.finish <> AsyncDecoupledCrossing(from_clock, from_reset, from_source.finish, to_clock, to_reset, depth, sync)
|
||||
from_source.grant <> AsyncDecoupledCrossing(to_clock, to_reset, to_sink.grant, from_clock, from_reset, depth, sync)
|
||||
from_source.probe <> AsyncDecoupledCrossing(to_clock, to_reset, to_sink.probe, from_clock, from_reset, depth, sync)
|
||||
to_sink
|
||||
}
|
||||
}
|
||||
|
||||
object AsyncUTileLinkTo {
|
||||
def apply(to_clock: Clock, to_reset: Bool, source: ClientUncachedTileLinkIO, depth: Int = 8, sync: Int = 3): ClientUncachedTileLinkIO = {
|
||||
val scope = AsyncScope()
|
||||
AsyncClientUncachedTileLinkCrossing(scope.clock, scope.reset, source, to_clock, to_reset, depth, sync)
|
||||
}
|
||||
}
|
||||
|
||||
object AsyncUTileLinkFrom {
|
||||
def apply(from_clock: Clock, from_reset: Bool, from_source: ClientUncachedTileLinkIO, depth: Int = 8, sync: Int = 3): ClientUncachedTileLinkIO = {
|
||||
val scope = AsyncScope()
|
||||
AsyncClientUncachedTileLinkCrossing(from_clock, from_reset, from_source, scope.clock, scope.reset, depth, sync)
|
||||
}
|
||||
}
|
||||
|
||||
object AsyncTileLinkTo {
|
||||
def apply(to_clock: Clock, to_reset: Bool, source: ClientTileLinkIO, depth: Int = 8, sync: Int = 3): ClientTileLinkIO = {
|
||||
val scope = AsyncScope()
|
||||
AsyncClientTileLinkCrossing(scope.clock, scope.reset, source, to_clock, to_reset, depth, sync)
|
||||
}
|
||||
}
|
||||
|
||||
object AsyncTileLinkFrom {
|
||||
def apply(from_clock: Clock, from_reset: Bool, from_source: ClientTileLinkIO, depth: Int = 8, sync: Int = 3): ClientTileLinkIO = {
|
||||
val scope = AsyncScope()
|
||||
AsyncClientTileLinkCrossing(from_clock, from_reset, from_source, scope.clock, scope.reset, depth, sync)
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user