add multiclock support to Coreplex

2016-09-21 16:54:35 -07:00
parent 8e63f4a1a5
commit 7afd630d3e
12 changed files with 442 additions and 204 deletions
--- a/src/main/scala/rocketchip/Configs.scala
+++ b/src/main/scala/rocketchip/Configs.scala
@ -40,7 +40,7 @@ class BasePlatformConfig extends Config(
            idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
        }
        case BuildCoreplex =>
-          (p: Parameters, c: CoreplexConfig) => Module(new DefaultCoreplex(p, c))
+          (c: CoreplexConfig, p: Parameters) => uncore.tilelink2.LazyModule(new DefaultCoreplex(c)(p)).module
        case NExtTopInterrupts => 2
        // Note that PLIC asserts that this is > 0.
        case AsyncDebugBus => false