add multiclock support to Coreplex

src/main/scala/rocketchip/Configs.scala

@@ -40,7 +40,7 @@ class BasePlatformConfig extends Config(
             idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
         }
         case BuildCoreplex =>
-          (p: Parameters, c: CoreplexConfig) => Module(new DefaultCoreplex(p, c))
+          (c: CoreplexConfig, p: Parameters) => uncore.tilelink2.LazyModule(new DefaultCoreplex(c)(p)).module
         case NExtTopInterrupts => 2
         // Note that PLIC asserts that this is > 0.
         case AsyncDebugBus => false