riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

add multiclock support to Coreplex

Browse Source
This commit is contained in:
Yunsup Lee
2016-09-21 16:54:35 -07:00
parent 8e63f4a1a5
commit 7afd630d3e
12 changed files with 442 additions and 204 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/groundtest/Configs.scala
View File

@ -83,7 +83,7 @@ class PCIeMockupTestConfig extends Config(
class WithGroundTest extends Config(
(pname, site, here) => pname match {
case BuildCoreplex =>
(p: Parameters, c: CoreplexConfig) => Module(new GroundTestCoreplex(p, c))
(c: CoreplexConfig, p: Parameters) => uncore.tilelink2.LazyModule(new GroundTestCoreplex(c)(p)).module
case TLKey("L1toL2") => {
val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
TileLinkParameters(