add multiclock support to Coreplex

src/main/scala/groundtest/Configs.scala

@@ -83,7 +83,7 @@ class PCIeMockupTestConfig extends Config(
 class WithGroundTest extends Config(
   (pname, site, here) => pname match {
     case BuildCoreplex =>
-      (p: Parameters, c: CoreplexConfig) => Module(new GroundTestCoreplex(p, c))
+      (c: CoreplexConfig, p: Parameters) => uncore.tilelink2.LazyModule(new GroundTestCoreplex(c)(p)).module
     case TLKey("L1toL2") => {
       val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
       TileLinkParameters(

src/main/scala/groundtest/Coreplex.scala

@@ -2,8 +2,15 @@ package groundtest
 
 import Chisel._
 import cde.{Parameters}
-import coreplex.{CoreplexConfig, DefaultCoreplex}
+import coreplex._
 
-class GroundTestCoreplex(tp: Parameters, tc: CoreplexConfig) extends DefaultCoreplex(tp, tc) {
-  io.success := tileList.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
+class GroundTestCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplex(c)(p) {
+  override lazy val module = Module(new GroundTestCoreplexModule(c, this, new GroundTestCoreplexBundle(c)(p))(p))
+}
+
+class GroundTestCoreplexBundle(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplexBundle(c)(p)
+
+class GroundTestCoreplexModule[+L <: GroundTestCoreplex, +B <: GroundTestCoreplexBundle](
+    c: CoreplexConfig, l: L, b: => B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p) with DirectConnection {
+  io.success := tiles.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
 }

src/main/scala/groundtest/Tile.scala

@@ -101,7 +101,7 @@ class GroundTestTile(resetSignal: Bool)
                     extends Tile(resetSignal = resetSignal)(p)
                     with HasGroundTestParameters {
 
-  override val io = new TileIO {
+  override val io = new TileIO(bc) {
     val success = Bool(OUTPUT)
   }