add multiclock support to Coreplex
This commit is contained in:
Yunsup Lee
@ -4,165 +4,81 @@ import Chisel._
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import cde.{Parameters, Field}
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import junctions._
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import uncore.tilelink._
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import uncore.coherence._
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import uncore.agents._
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import uncore.devices._
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import uncore.util._
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import uncore.converters._
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import rocket._
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import rocket.Util._
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/** Number of memory channels */
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case object NMemoryChannels extends Field[Int]
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/** Number of banks per memory channel */
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case object NBanksPerMemoryChannel extends Field[Int]
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/** Least significant bit of address used for bank partitioning */
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case object BankIdLSB extends Field[Int]
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/** Function for building some kind of coherence manager agent */
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case object BuildL2CoherenceManager extends Field[(Int, Parameters) => CoherenceAgent]
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/** Function for building some kind of tile connected to a reset signal */
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case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
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/** The file to read the BootROM contents from */
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case object BootROMFile extends Field[String]
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trait DirectConnection {
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val tiles: Seq[Tile]
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val uncoreTileIOs: Seq[TileIO]
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trait HasCoreplexParameters {
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implicit val p: Parameters
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lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
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lazy val lsb = p(BankIdLSB)
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lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
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lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" })
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lazy val outermostMMIOParams = p.alterPartial({ case TLId => "MMIO_Outermost" })
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lazy val globalAddrMap = p(rocketchip.GlobalAddrMap)
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}
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val tlBuffering = TileLinkDepths(1,1,2,2,0)
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val ultBuffering = UncachedTileLinkDepths(1,2)
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case class CoreplexConfig(
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nTiles: Int,
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nExtInterrupts: Int,
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nSlaves: Int,
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nMemChannels: Int,
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hasSupervisor: Boolean,
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hasExtMMIOPort: Boolean)
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{
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val plicKey = PLICConfig(nTiles, hasSupervisor, nExtInterrupts, 0)
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}
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(tiles zip uncoreTileIOs) foreach { case (tile, uncore) =>
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(uncore.cached zip tile.io.cached) foreach { case (u, t) => u <> TileLinkEnqueuer(t, tlBuffering)(t.p) }
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(uncore.uncached zip tile.io.uncached) foreach { case (u, t) => u <> TileLinkEnqueuer(t, ultBuffering)(t.p) }
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tile.io.slave.foreach { _ <> TileLinkEnqueuer(uncore.slave.get, 1)(uncore.slave.get.p) }
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abstract class Coreplex(implicit val p: Parameters, implicit val c: CoreplexConfig) extends Module
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with HasCoreplexParameters {
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class CoreplexIO(implicit val p: Parameters, implicit val c: CoreplexConfig) extends Bundle {
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val master = new Bundle {
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val mem = Vec(c.nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))
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val mmio = c.hasExtMMIOPort.option(new ClientUncachedTileLinkIO()(outermostMMIOParams))
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}
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val slave = Vec(c.nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip
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val interrupts = Vec(c.nExtInterrupts, Bool()).asInput
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val debug = new DebugBusIO()(p).flip
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val clint = Vec(c.nTiles, new CoreplexLocalInterrupts).asInput
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val success = Bool(OUTPUT)
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val resetVector = UInt(INPUT, p(XLen))
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}
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tile.io.interrupts <> uncore.interrupts
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val io = new CoreplexIO
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}
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class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp, tc) {
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// Coreplex doesn't know when to stop running
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io.success := Bool(false)
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// Build a set of Tiles
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val tileResets = Wire(Vec(tc.nTiles, Bool()))
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val tileList = p(BuildTiles).zip(tileResets).map {
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case (tile, rst) => tile(rst, p)
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}
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val nCachedPorts = tileList.map(tile => tile.io.cached.size).reduce(_ + _)
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val nUncachedPorts = tileList.map(tile => tile.io.uncached.size).reduce(_ + _)
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val nBanks = tc.nMemChannels * nBanksPerMemChannel
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// Build an uncore backing the Tiles
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buildUncore(p.alterPartial({
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case HastiId => "TL"
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case TLId => "L1toL2"
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case NCachedTileLinkPorts => nCachedPorts
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case NUncachedTileLinkPorts => nUncachedPorts
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}))
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def buildUncore(implicit p: Parameters) = {
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// Create a simple L1toL2 NoC between the tiles and the banks of outer memory
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// Cached ports are first in client list, making sharerToClientId just an indentity function
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// addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
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def sharerToClientId(sharerId: UInt) = sharerId
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def addrToBank(addr: UInt): UInt = if (nBanks == 0) UInt(0) else {
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val isMemory = globalAddrMap.isInRegion("mem", addr << log2Up(p(CacheBlockBytes)))
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Mux(isMemory, addr.extract(lsb + log2Ceil(nBanks) - 1, lsb), UInt(nBanks))
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}
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val preBuffering = TileLinkDepths(1,1,2,2,0)
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val l1tol2net = Module(new PortedTileLinkCrossbar(addrToBank, sharerToClientId, preBuffering))
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// Create point(s) of coherence serialization
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val managerEndpoints = List.tabulate(nBanks){id => p(BuildL2CoherenceManager)(id, p)}
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managerEndpoints.flatMap(_.incoherent).foreach(_ := Bool(false))
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val mmioManager = Module(new MMIOTileLinkManager()(p.alterPartial({
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case TLId => "L1toL2"
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMMIO"
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})))
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// Wire the tiles to the TileLink client ports of the L1toL2 network,
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// and coherence manager(s) to the other side
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l1tol2net.io.clients_cached <> tileList.map(_.io.cached).flatten
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l1tol2net.io.clients_uncached <> tileList.map(_.io.uncached).flatten ++ io.slave
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l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner
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// Create a converter between TileLinkIO and MemIO for each channel
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val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, tc.nMemChannels)(outermostParams))
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val outerTLParams = p.alterPartial({ case TLId => "L2toMC" })
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val backendBuffering = TileLinkDepths(0,0,0,0,0)
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for ((bank, icPort) <- managerEndpoints zip mem_ic.io.in) {
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val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
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unwrap.io.in <> TileLinkEnqueuer(bank.outerTL, backendBuffering)(outerTLParams)
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TileLinkWidthAdapter(icPort, unwrap.io.out)
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}
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io.master.mem <> mem_ic.io.out
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buildMMIONetwork(TileLinkEnqueuer(mmioManager.io.outer, 1))(
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p.alterPartial({case TLId => "L2toMMIO"}))
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}
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def buildMMIONetwork(mmio: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
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val ioAddrMap = globalAddrMap.subMap("io")
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val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap))
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mmioNetwork.io.in.head <> mmio
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val plic = Module(new PLIC(c.plicKey))
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plic.io.tl <> mmioNetwork.port("int:plic")
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for (i <- 0 until io.interrupts.size) {
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val gateway = Module(new LevelGateway)
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gateway.io.interrupt := io.interrupts(i)
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plic.io.devices(i) <> gateway.io.plic
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}
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val debugModule = Module(new DebugModule)
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debugModule.io.tl <> mmioNetwork.port("int:debug")
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debugModule.io.db <> io.debug
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// connect coreplex-internal interrupts to tiles
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for (((tile, tileReset), i) <- (tileList zip tileResets) zipWithIndex) {
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tileReset := reset // TODO should tiles be reset separately from coreplex?
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tile.io.interrupts := io.clint(i)
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tile.io.interrupts.meip := plic.io.harts(plic.cfg.context(i, 'M'))
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tile.io.interrupts.seip.foreach(_ := plic.io.harts(plic.cfg.context(i, 'S')))
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tile.io.interrupts.debug := debugModule.io.debugInterrupts(i)
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tile.io.hartid := i
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tile.io.resetVector := io.resetVector
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}
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val tileSlavePorts = (0 until tc.nTiles) map (i => s"int:dmem$i") filter (ioAddrMap contains _)
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for ((t, m) <- (tileList.map(_.io.slave).flatten) zip (tileSlavePorts map (mmioNetwork port _)))
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t <> TileLinkEnqueuer(m, 1)
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io.master.mmio.foreach { _ <> mmioNetwork.port("ext") }
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tile.io.hartid := uncore.hartid
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tile.io.resetVector := uncore.resetVector
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}
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}
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class DefaultCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplex(c)(p) {
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override lazy val module = Module(new DefaultCoreplexModule(c, this, new DefaultCoreplexBundle(c)(p))(p))
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}
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class DefaultCoreplexBundle(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplexBundle(c)(p)
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class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle](
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c: CoreplexConfig, l: L, b: => B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p)
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with DirectConnection
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/////
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trait TileClockResetBundle {
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val c: CoreplexConfig
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val trcs = Vec(c.nTiles, new Bundle {
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val clock = Clock(INPUT)
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val reset = Bool(INPUT)
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})
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}
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trait AsyncConnection {
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val io: TileClockResetBundle
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val tiles: Seq[Tile]
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val uncoreTileIOs: Seq[TileIO]
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(tiles, uncoreTileIOs, io.trcs).zipped foreach { case (tile, uncore, trc) =>
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tile.clock := trc.clock
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tile.reset := trc.reset
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(uncore.cached zip tile.io.cached) foreach { case (u, t) => u <> AsyncTileLinkFrom(trc.clock, trc.reset, t) }
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(uncore.uncached zip tile.io.uncached) foreach { case (u, t) => u <> AsyncUTileLinkFrom(trc.clock, trc.reset, t) }
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tile.io.slave.foreach { _ <> AsyncUTileLinkTo(trc.clock, trc.reset, uncore.slave.get)}
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val ti = tile.io.interrupts
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val ui = uncore.interrupts
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ti.debug := LevelSyncTo(trc.clock, ui.debug)
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ti.mtip := LevelSyncTo(trc.clock, ui.mtip)
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ti.msip := LevelSyncTo(trc.clock, ui.msip)
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ti.meip := LevelSyncTo(trc.clock, ui.meip)
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ti.seip.foreach { _ := LevelSyncTo(trc.clock, ui.seip.get) }
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tile.io.hartid := uncore.hartid
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tile.io.resetVector := uncore.resetVector
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}
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}
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class MultiClockCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplex(c)(p) {
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override lazy val module = Module(new MultiClockCoreplexModule(c, this, new MultiClockCoreplexBundle(c)(p))(p))
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}
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class MultiClockCoreplexBundle(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplexBundle(c)(p)
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with TileClockResetBundle
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class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle](
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c: CoreplexConfig, l: L, b: => B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p)
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with AsyncConnection
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