riscv/rocket-chip
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remove unnecessary whitespace. Fix grammar.

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Megan Wachs 2017-06-05 16:18:57 -07:00 committed by GitHub
parent 8440c4b1c4
commit 7afd5e6070
1 changed files with 1 additions and 2 deletions
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src/main/scala/util/PlusArg.scala
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@ -9,7 +9,6 @@ class plusarg_reader(val format: String, val default: Int, val docstring: String
val io = new Bundle { val io = new Bundle {
val out = UInt(OUTPUT, width = 32) val out = UInt(OUTPUT, width = 32)
} }
} }
object PlusArg object PlusArg
@ -17,7 +16,7 @@ object PlusArg
// PlusArg("foo") will return 42.U if the simulation is run with +foo=42 // PlusArg("foo") will return 42.U if the simulation is run with +foo=42
// Do not use this as an initial register value. The value is set in an // Do not use this as an initial register value. The value is set in an
// initial block and thus accessing it from another initial is racey. // initial block and thus accessing it from another initial is racey.
// Add a docstring to document the arg, which can be dumped in elaboration // Add a docstring to document the arg, which can be dumped in an elaboration
// pass. // pass.
def apply(name: String, default: Int = 0, docstring: String = ""): UInt = def apply(name: String, default: Int = 0, docstring: String = ""): UInt =