Add RV32 support

rocket/src/main/scala/csr.scala

@@ -162,13 +162,14 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
   val reg_tohost = Reg(init=Bits(0, xLen))
   val reg_fromhost = Reg(init=Bits(0, xLen))
   val reg_stats = Reg(init=Bool(false))
-  val reg_time = Reg(UInt(width = xLen))
-  val reg_instret = WideCounter(xLen, io.retire)
-  val reg_cycle: UInt = if (enableCommitLog) { reg_instret } else { WideCounter(xLen) }
   val reg_uarch_counters = io.uarch_counters.map(WideCounter(xLen, _))
   val reg_fflags = Reg(UInt(width = 5))
   val reg_frm = Reg(UInt(width = 3))
 
+  val reg_time = Reg(UInt(width = 64)) // regardless of XLEN
+  val reg_instret = WideCounter(64, io.retire)
+  val reg_cycle: UInt = if (enableCommitLog) { reg_instret } else { WideCounter(64) }
+
   val mip = Wire(init=reg_mip)
   mip.host := (reg_fromhost =/= 0)
   mip.rocc := io.rocc.interrupt
@@ -277,6 +278,20 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
     read_mapping += CSRs.msinstret_delta -> UInt(0)
   }
 
+  if (xLen == 32) {
+    read_mapping += CSRs.mtimeh -> (reg_time >> 32)
+    read_mapping += CSRs.mcycleh -> (reg_cycle >> 32)
+    read_mapping += CSRs.minstreth -> (reg_instret >> 32)
+    read_mapping += CSRs.mutime_deltah -> UInt(0)
+    read_mapping += CSRs.mucycle_deltah -> UInt(0)
+    read_mapping += CSRs.muinstret_deltah -> UInt(0)
+    if (usingVM) {
+      read_mapping += CSRs.mstime_deltah -> UInt(0)
+      read_mapping += CSRs.mscycle_deltah -> UInt(0)
+      read_mapping += CSRs.msinstret_deltah -> UInt(0)
+    }
+  }
+
   for (i <- 0 until nCustomMrwCsrs) {
     val addr = 0xff0 + i
     require(addr < (1 << CSR.ADDRSZ))

rocket/src/main/scala/fpu.scala

@@ -138,15 +138,15 @@ class FPUDecoder extends Module
   sigs zip decoder map {case(s,d) => s := d}
 }
 
-class FPUIO extends Bundle {
+class FPUIO(implicit p: Parameters) extends CoreBundle {
   val inst = Bits(INPUT, 32)
-  val fromint_data = Bits(INPUT, 64)
+  val fromint_data = Bits(INPUT, xLen)
 
   val fcsr_rm = Bits(INPUT, FPConstants.RM_SZ)
   val fcsr_flags = Valid(Bits(width = FPConstants.FLAGS_SZ))
 
   val store_data = Bits(OUTPUT, 64)
-  val toint_data = Bits(OUTPUT, 64)
+  val toint_data = Bits(OUTPUT, xLen)
 
   val dmem_resp_val = Bool(INPUT)
   val dmem_resp_type = Bits(INPUT, 3)
@@ -414,6 +414,7 @@ class FPUFMAPipe(val latency: Int, expWidth: Int, sigWidth: Int) extends Module
 }
 
 class FPU(implicit p: Parameters) extends CoreModule()(p) {
+  require(xLen == 64, "RV32 Rocket FP support missing")
   val io = new FPUIO
 
   val ex_reg_valid = Reg(next=io.valid, init=Bool(false))

rocket/src/main/scala/idecode.scala

@@ -6,21 +6,11 @@ import Chisel._
 import Instructions._
 import uncore.constants.MemoryOpConstants._
 import ALU._
+import cde.Parameters
 
-abstract trait DecodeConstants
+abstract trait DecodeConstants extends HasCoreParameters
 {
-  val xpr64 = Y
+  val xpr64 = Bool(xLen == 64)
-
-  val decode_default: List[BitPat] =
-                //               jal                                                               renf1             fence.i
-                //               | jalr                                                            | renf2           |
-                //         fp_val| | renx2                                                         | | renf3         |
-                //         | rocc| | | renx1     s_alu1                          mem_val           | | | wfd         | 
-                //   val   | | br| | | | s_alu2  |       imm    dw     alu       | mem_cmd mem_type| | | | div       | 
-                //   |     | | | | | | | |       |       |      |      |         | |         |     | | | | | wxd     | fence
-                //   |     | | | | | | | |       |       |      |      |         | |         |     | | | | | | csr   | | amo
-                //   |     | | | | | | | |       |       |      |      |         | |         |     | | | | | | |     | | |
-                List(N,    X,X,X,X,X,X,X,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, X,X,X,X,X,X,CSR.X,X,X,X)
 
   val table: Array[(BitPat, List[BitPat])]
 }
@@ -53,8 +43,19 @@ class IntCtrlSigs extends Bundle {
   val fence = Bool()
   val amo = Bool()
 
+  def default: List[BitPat] =
+                //               jal                                                               renf1             fence.i
+                //               | jalr                                                            | renf2           |
+                //         fp_val| | renx2                                                         | | renf3         |
+                //         | rocc| | | renx1     s_alu1                          mem_val           | | | wfd         | 
+                //   val   | | br| | | | s_alu2  |       imm    dw     alu       | mem_cmd mem_type| | | | div       | 
+                //   |     | | | | | | | |       |       |      |      |         | |         |     | | | | | wxd     | fence
+                //   |     | | | | | | | |       |       |      |      |         | |         |     | | | | | | csr   | | amo
+                //   |     | | | | | | | |       |       |      |      |         | |         |     | | | | | | |     | | |
+                List(N,    X,X,X,X,X,X,X,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, X,X,X,X,X,X,CSR.X,X,X,X)
+
   def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = {
-    val decoder = DecodeLogic(inst, XDecode.decode_default, table)
+    val decoder = DecodeLogic(inst, default, table)
     val sigs = Seq(legal, fp, rocc, branch, jal, jalr, rxs2, rxs1, sel_alu2,
                    sel_alu1, sel_imm, alu_dw, alu_fn, mem, mem_cmd, mem_type,
                    rfs1, rfs2, rfs3, wfd, div, wxd, csr, fence_i, fence, amo)
@@ -63,7 +64,7 @@ class IntCtrlSigs extends Bundle {
   }
 }
 
-object XDecode extends DecodeConstants
+class XDecode(implicit val p: Parameters) extends DecodeConstants
 {
   val table: Array[(BitPat, List[BitPat])] = Array(
                 //               jal                                                               renf1             fence.i
@@ -183,7 +184,7 @@ object XDecode extends DecodeConstants
     CSRRCI->    List(Y,    N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD,   N,M_X,      MT_X, N,N,N,N,N,Y,CSR.C,N,N,N))
 }
 
-object FDecode extends DecodeConstants
+class FDecode(implicit val p: Parameters) extends DecodeConstants
 {
   val table: Array[(BitPat, List[BitPat])] = Array(
                 //               jal                                                               renf1             fence.i
@@ -223,15 +224,15 @@ object FDecode extends DecodeConstants
     FCLASS_S->  List(Y,    Y,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
     FCLASS_D->  List(Y,    Y,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
     FMV_X_S->   List(Y,    Y,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
-    FMV_X_D->   List(Y,    Y,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
+    FMV_X_D->   List(xpr64,Y,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
     FCVT_W_S->  List(Y,    Y,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
     FCVT_W_D->  List(Y,    Y,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
     FCVT_WU_S-> List(Y,    Y,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
     FCVT_WU_D-> List(Y,    Y,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
-    FCVT_L_S->  List(Y,    Y,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
+    FCVT_L_S->  List(xpr64,Y,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
-    FCVT_L_D->  List(Y,    Y,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
+    FCVT_L_D->  List(xpr64,Y,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
-    FCVT_LU_S-> List(Y,    Y,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
+    FCVT_LU_S-> List(xpr64,Y,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
-    FCVT_LU_D-> List(Y,    Y,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
+    FCVT_LU_D-> List(xpr64,Y,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
     FEQ_S->     List(Y,    Y,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, Y,Y,N,N,N,Y,CSR.N,N,N,N),
     FEQ_D->     List(Y,    Y,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, Y,Y,N,N,N,Y,CSR.N,N,N,N),
     FLT_S->     List(Y,    Y,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, Y,Y,N,N,N,Y,CSR.N,N,N,N),
@@ -239,22 +240,22 @@ object FDecode extends DecodeConstants
     FLE_S->     List(Y,    Y,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, Y,Y,N,N,N,Y,CSR.N,N,N,N),
     FLE_D->     List(Y,    Y,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, Y,Y,N,N,N,Y,CSR.N,N,N,N),
     FMV_S_X->   List(Y,    Y,N,N,N,N,N,Y,A2_X,   A1_RS1, IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
-    FMV_D_X->   List(Y,    Y,N,N,N,N,N,Y,A2_X,   A1_RS1, IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
+    FMV_D_X->   List(xpr64,Y,N,N,N,N,N,Y,A2_X,   A1_RS1, IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
     FCVT_S_W->  List(Y,    Y,N,N,N,N,N,Y,A2_X,   A1_RS1, IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
     FCVT_D_W->  List(Y,    Y,N,N,N,N,N,Y,A2_X,   A1_RS1, IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
     FCVT_S_WU-> List(Y,    Y,N,N,N,N,N,Y,A2_X,   A1_RS1, IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
     FCVT_D_WU-> List(Y,    Y,N,N,N,N,N,Y,A2_X,   A1_RS1, IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
-    FCVT_S_L->  List(Y,    Y,N,N,N,N,N,Y,A2_X,   A1_RS1, IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
+    FCVT_S_L->  List(xpr64,Y,N,N,N,N,N,Y,A2_X,   A1_RS1, IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
-    FCVT_D_L->  List(Y,    Y,N,N,N,N,N,Y,A2_X,   A1_RS1, IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
+    FCVT_D_L->  List(xpr64,Y,N,N,N,N,N,Y,A2_X,   A1_RS1, IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
-    FCVT_S_LU-> List(Y,    Y,N,N,N,N,N,Y,A2_X,   A1_RS1, IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
+    FCVT_S_LU-> List(xpr64,Y,N,N,N,N,N,Y,A2_X,   A1_RS1, IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
-    FCVT_D_LU-> List(Y,    Y,N,N,N,N,N,Y,A2_X,   A1_RS1, IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
+    FCVT_D_LU-> List(xpr64,Y,N,N,N,N,N,Y,A2_X,   A1_RS1, IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
     FLW->       List(Y,    Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD,   Y,M_XRD,    MT_W, N,N,N,Y,N,N,CSR.N,N,N,N),
     FLD->       List(Y,    Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD,   Y,M_XRD,    MT_D, N,N,N,Y,N,N,CSR.N,N,N,N),
     FSW->       List(Y,    Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD,   Y,M_XWR,    MT_W, N,Y,N,N,N,N,CSR.N,N,N,N),
     FSD->       List(Y,    Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD,   Y,M_XWR,    MT_D, N,Y,N,N,N,N,CSR.N,N,N,N))
 }
 
-object FDivSqrtDecode extends DecodeConstants
+class FDivSqrtDecode(implicit val p: Parameters) extends DecodeConstants
 {
   val table: Array[(BitPat, List[BitPat])] = Array(
     FDIV_S->    List(Y,    Y,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
@@ -263,7 +264,7 @@ object FDivSqrtDecode extends DecodeConstants
     FSQRT_D->   List(Y,    Y,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  FN_X,     N,M_X,      MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N))
 }
 
-object RoCCDecode extends DecodeConstants
+class RoCCDecode(implicit val p: Parameters) extends DecodeConstants
 {
   val table: Array[(BitPat, List[BitPat])] = Array(
                         //               jal                                                               renf1             fence.i

rocket/src/main/scala/nbdcache.scala

@@ -161,8 +161,8 @@ class IOMSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   val req_cmd_sc = req.cmd === M_XSC
   val grant_word = Reg(UInt(width = wordBits))
 
-  val storegen = new StoreGen(req.typ, req.addr, req.data, 8)
+  val storegen = new StoreGen(req.typ, req.addr, req.data, wordBits/8)
-  val loadgen = new LoadGen(req.typ, req.addr, grant_word, req_cmd_sc, 8)
+  val loadgen = new LoadGen(req.typ, req.addr, grant_word, req_cmd_sc, wordBits/8)
 
   val beat_offset = req.addr(beatOffBits - 1, wordOffBits)
   val beat_mask = (storegen.mask << Cat(beat_offset, UInt(0, wordOffBits)))
@@ -814,7 +814,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
     s2_req.cmd := s1_req.cmd
   }
 
-  val misaligned = new StoreGen(s1_req.typ, s1_req.addr, UInt(0), 8).misaligned
+  val misaligned = new StoreGen(s1_req.typ, s1_req.addr, UInt(0), wordBits/8).misaligned
   io.cpu.xcpt.ma.ld := s1_read && misaligned
   io.cpu.xcpt.ma.st := s1_write && misaligned
   io.cpu.xcpt.pf.ld := s1_read && dtlb.io.resp.xcpt_ld
@@ -1013,7 +1013,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   // load data subword mux/sign extension
   val s2_data_word_prebypass = s2_data_uncorrected >> Cat(s2_word_idx, Bits(0,log2Up(coreDataBits)))
   val s2_data_word = Mux(s2_store_bypass, s2_store_bypass_data, s2_data_word_prebypass)
-  val loadgen = new LoadGen(s2_req.typ, s2_req.addr, s2_data_word, s2_sc, 8)
+  val loadgen = new LoadGen(s2_req.typ, s2_req.addr, s2_data_word, s2_sc, wordBits/8)
   
   amoalu.io.addr := s2_req.addr
   amoalu.io.cmd := s2_req.cmd

rocket/src/main/scala/rocket.scala

@@ -45,8 +45,9 @@ trait HasCoreParameters extends HasAddrMapParameters {
   val coreDataBits = xLen
   val coreDataBytes = coreDataBits/8
   val coreDCacheReqTagBits = 7 + (2 + (if(!usingRoCC) 0 else 1))
-  val coreMaxAddrBits = math.max(ppnBits,vpnBits+1) + pgIdxBits
+  val vpnBitsExtended = vpnBits + (vaddrBits < xLen).toInt
-  val vaddrBitsExtended = vaddrBits + (vaddrBits < xLen).toInt
+  val vaddrBitsExtended = vpnBitsExtended + pgIdxBits
+  val coreMaxAddrBits = paddrBits max vaddrBitsExtended
   val mmioBase = p(MMIOBase)
   val nCustomMrwCsrs = p(NCustomMRWCSRs)
   val roccCsrs = if (p(BuildRoCC).isEmpty) Nil
@@ -118,10 +119,10 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
     val rocc = new RoCCInterface().flip
   }
 
-  var decode_table = XDecode.table
+  var decode_table = new XDecode().table
-  if (usingFPU) decode_table ++= FDecode.table
+  if (usingFPU) decode_table ++= new FDecode().table
-  if (usingFPU && usingFDivSqrt) decode_table ++= FDivSqrtDecode.table
+  if (usingFPU && usingFDivSqrt) decode_table ++= new FDivSqrtDecode().table
-  if (usingRoCC) decode_table ++= RoCCDecode.table
+  if (usingRoCC) decode_table ++= new RoCCDecode().table
 
   val ex_ctrl = Reg(new IntCtrlSigs)
   val mem_ctrl = Reg(new IntCtrlSigs)
@@ -312,7 +313,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
     Mux(mem_ctrl.branch && mem_br_taken, ImmGen(IMM_SB, mem_reg_inst),
     Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst), SInt(4)))
   val mem_int_wdata = Mux(mem_ctrl.jalr, mem_br_target, mem_reg_wdata.toSInt).toUInt
-  val mem_npc = (Mux(mem_ctrl.jalr, Cat(vaSign(mem_reg_wdata, mem_reg_wdata), mem_reg_wdata(vaddrBits-1,0)).toSInt, mem_br_target) & SInt(-2)).toUInt
+  val mem_npc = (Mux(mem_ctrl.jalr, encodeVirtualAddress(mem_reg_wdata, mem_reg_wdata).toSInt, mem_br_target) & SInt(-2)).toUInt
   val mem_wrong_npc = mem_npc =/= ex_reg_pc || !ex_reg_valid
   val mem_npc_misaligned = mem_npc(1)
   val mem_misprediction = mem_wrong_npc && mem_reg_valid && (mem_ctrl.branch || mem_ctrl.jalr || mem_ctrl.jal)
@@ -531,7 +532,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
   io.dmem.req.bits.cmd  := ex_ctrl.mem_cmd
   io.dmem.req.bits.typ  := ex_ctrl.mem_type
   io.dmem.req.bits.phys := Bool(false)
-  io.dmem.req.bits.addr := Cat(vaSign(ex_rs(0), alu.io.adder_out), alu.io.adder_out(vaddrBits-1,0)).toUInt
+  io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out)
   io.dmem.req.bits.tag := Cat(ex_waddr, ex_ctrl.fp)
   io.dmem.req.bits.data := Mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2)
   require(coreDCacheReqTagBits >= 6)
@@ -545,7 +546,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
   io.rocc.cmd.bits.rs2 := wb_reg_rs2
 
   if (enableCommitLog) {
-    val pc = Wire(SInt(width=64))
+    val pc = Wire(SInt(width=xLen))
     pc := wb_reg_pc
     val inst = wb_reg_inst
     val rd = RegNext(RegNext(RegNext(id_waddr)))
@@ -575,7 +576,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
   }
   else {
     printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
-         io.host.id, csr.io.time(32,0), wb_valid, wb_reg_pc,
+         io.host.id, csr.io.time(31,0), wb_valid, wb_reg_pc,
          Mux(rf_wen, rf_waddr, UInt(0)), rf_wdata, rf_wen,
          wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs(0))),
          wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs(1))),
@@ -588,14 +589,15 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
   def checkHazards(targets: Seq[(Bool, UInt)], cond: UInt => Bool) =
     targets.map(h => h._1 && cond(h._2)).reduce(_||_)
 
-  def vaSign(a0: UInt, ea: UInt) = {
+  def encodeVirtualAddress(a0: UInt, ea: UInt) = if (xLen == 32) ea else {
     // efficient means to compress 64-bit VA into vaddrBits+1 bits
     // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1))
     val a = a0 >> vaddrBits-1
-    val e = ea(vaddrBits,vaddrBits-1)
+    val e = ea(vaddrBits,vaddrBits-1).toSInt
-    Mux(a === UInt(0) || a === UInt(1), e =/= UInt(0),
+    val msb =
-    Mux(a.toSInt === SInt(-1) || a.toSInt === SInt(-2), e.toSInt === SInt(-1),
+      Mux(a === UInt(0) || a === UInt(1), e =/= SInt(0),
-    e(0)))
+      Mux(a.toSInt === SInt(-1) || a.toSInt === SInt(-2), e === SInt(-1), e(0)))
+    Cat(msb, ea(vaddrBits-1,0))
   }
 
   class Scoreboard(n: Int)

rocket/src/main/scala/tlb.scala

@@ -11,7 +11,7 @@ import uncore.PseudoLRU
 
 case object NTLBEntries extends Field[Int]
 
-trait HasTLBParameters extends HasAddrMapParameters {
+trait HasTLBParameters extends HasCoreParameters {
   val entries = p(NTLBEntries)
   val camAddrBits = log2Ceil(entries)
   val camTagBits = asIdBits + vpnBits
@@ -57,7 +57,7 @@ class RocketCAM(implicit p: Parameters) extends TLBModule()(p) {
 
 class TLBReq(implicit p: Parameters) extends CoreBundle()(p) {
   val asid = UInt(width = asIdBits)
-  val vpn = UInt(width = vpnBits+1)
+  val vpn = UInt(width = vpnBitsExtended)
   val passthrough = Bool()
   val instruction = Bool()
   val store = Bool()
@@ -138,7 +138,9 @@ class TLB(implicit p: Parameters) extends TLBModule()(p) {
   val x_array = Mux(priv_s, sx_array.toBits, ux_array.toBits)
 
   val vm_enabled = io.ptw.status.vm(3) && priv_uses_vm && !io.req.bits.passthrough
-  val bad_va = io.req.bits.vpn(vpnBits) =/= io.req.bits.vpn(vpnBits-1)
+  val bad_va =
+    if (vpnBits == vpnBitsExtended) Bool(false)
+    else io.req.bits.vpn(vpnBits) =/= io.req.bits.vpn(vpnBits-1)
   // it's only a store hit if the dirty bit is set
   val tag_hits = tag_cam.io.hits & (dirty_array.toBits | ~Mux(io.req.bits.store, w_array, UInt(0)))
   val tag_hit = tag_hits.orR