riscv/rocket-chip
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Add RV32 support

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This commit is contained in:
Andrew Waterman
2016-03-10 17:32:00 -08:00
parent 82c595d11a
commit 7ae44d4905
6 changed files with 77 additions and 56 deletions
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32
rocket/src/main/scala/rocket.scala
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@ -45,8 +45,9 @@ trait HasCoreParameters extends HasAddrMapParameters {
val coreDataBits = xLen
val coreDataBytes = coreDataBits/8
val coreDCacheReqTagBits = 7 + (2 + (if(!usingRoCC) 0 else 1))
val coreMaxAddrBits = math.max(ppnBits,vpnBits+1) + pgIdxBits
val vaddrBitsExtended = vaddrBits + (vaddrBits < xLen).toInt
val vpnBitsExtended = vpnBits + (vaddrBits < xLen).toInt
val vaddrBitsExtended = vpnBitsExtended + pgIdxBits
val coreMaxAddrBits = paddrBits max vaddrBitsExtended
val mmioBase = p(MMIOBase)
val nCustomMrwCsrs = p(NCustomMRWCSRs)
val roccCsrs = if (p(BuildRoCC).isEmpty) Nil
@ -118,10 +119,10 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
val rocc = new RoCCInterface().flip
}
var decode_table = XDecode.table
if (usingFPU) decode_table ++= FDecode.table
if (usingFPU && usingFDivSqrt) decode_table ++= FDivSqrtDecode.table
if (usingRoCC) decode_table ++= RoCCDecode.table
var decode_table = new XDecode().table
if (usingFPU) decode_table ++= new FDecode().table
if (usingFPU && usingFDivSqrt) decode_table ++= new FDivSqrtDecode().table
if (usingRoCC) decode_table ++= new RoCCDecode().table
val ex_ctrl = Reg(new IntCtrlSigs)
val mem_ctrl = Reg(new IntCtrlSigs)
@ -312,7 +313,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
Mux(mem_ctrl.branch && mem_br_taken, ImmGen(IMM_SB, mem_reg_inst),
Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst), SInt(4)))
val mem_int_wdata = Mux(mem_ctrl.jalr, mem_br_target, mem_reg_wdata.toSInt).toUInt
val mem_npc = (Mux(mem_ctrl.jalr, Cat(vaSign(mem_reg_wdata, mem_reg_wdata), mem_reg_wdata(vaddrBits-1,0)).toSInt, mem_br_target) & SInt(-2)).toUInt
val mem_npc = (Mux(mem_ctrl.jalr, encodeVirtualAddress(mem_reg_wdata, mem_reg_wdata).toSInt, mem_br_target) & SInt(-2)).toUInt
val mem_wrong_npc = mem_npc =/= ex_reg_pc || !ex_reg_valid
val mem_npc_misaligned = mem_npc(1)
val mem_misprediction = mem_wrong_npc && mem_reg_valid && (mem_ctrl.branch || mem_ctrl.jalr || mem_ctrl.jal)
@ -531,7 +532,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
io.dmem.req.bits.cmd := ex_ctrl.mem_cmd
io.dmem.req.bits.typ := ex_ctrl.mem_type
io.dmem.req.bits.phys := Bool(false)
io.dmem.req.bits.addr := Cat(vaSign(ex_rs(0), alu.io.adder_out), alu.io.adder_out(vaddrBits-1,0)).toUInt
io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out)
io.dmem.req.bits.tag := Cat(ex_waddr, ex_ctrl.fp)
io.dmem.req.bits.data := Mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2)
require(coreDCacheReqTagBits >= 6)
@ -545,7 +546,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
io.rocc.cmd.bits.rs2 := wb_reg_rs2
if (enableCommitLog) {
val pc = Wire(SInt(width=64))
val pc = Wire(SInt(width=xLen))
pc := wb_reg_pc
val inst = wb_reg_inst
val rd = RegNext(RegNext(RegNext(id_waddr)))
@ -575,7 +576,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
}
else {
printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
io.host.id, csr.io.time(32,0), wb_valid, wb_reg_pc,
io.host.id, csr.io.time(31,0), wb_valid, wb_reg_pc,
Mux(rf_wen, rf_waddr, UInt(0)), rf_wdata, rf_wen,
wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs(0))),
wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs(1))),
@ -588,14 +589,15 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
def checkHazards(targets: Seq[(Bool, UInt)], cond: UInt => Bool) =
targets.map(h => h._1 && cond(h._2)).reduce(_||_)
def vaSign(a0: UInt, ea: UInt) = {
def encodeVirtualAddress(a0: UInt, ea: UInt) = if (xLen == 32) ea else {
// efficient means to compress 64-bit VA into vaddrBits+1 bits
// (VA is bad if VA(vaddrBits) != VA(vaddrBits-1))
val a = a0 >> vaddrBits-1
val e = ea(vaddrBits,vaddrBits-1)
Mux(a === UInt(0) || a === UInt(1), e =/= UInt(0),
Mux(a.toSInt === SInt(-1) || a.toSInt === SInt(-2), e.toSInt === SInt(-1),
e(0)))
val e = ea(vaddrBits,vaddrBits-1).toSInt
val msb =
Mux(a === UInt(0) || a === UInt(1), e =/= SInt(0),
Mux(a.toSInt === SInt(-1) || a.toSInt === SInt(-2), e === SInt(-1), e(0)))
Cat(msb, ea(vaddrBits-1,0))
}
class Scoreboard(n: Int)