riscv/rocket-chip
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Add RV32 support

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This commit is contained in:
Andrew Waterman
2016-03-10 17:32:00 -08:00
parent 82c595d11a
commit 7ae44d4905
6 changed files with 77 additions and 56 deletions
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21
rocket/src/main/scala/csr.scala
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@ -162,13 +162,14 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
val reg_tohost = Reg(init=Bits(0, xLen))
val reg_fromhost = Reg(init=Bits(0, xLen))
val reg_stats = Reg(init=Bool(false))
val reg_time = Reg(UInt(width = xLen))
val reg_instret = WideCounter(xLen, io.retire)
val reg_cycle: UInt = if (enableCommitLog) { reg_instret } else { WideCounter(xLen) }
val reg_uarch_counters = io.uarch_counters.map(WideCounter(xLen, _))
val reg_fflags = Reg(UInt(width = 5))
val reg_frm = Reg(UInt(width = 3))
val reg_time = Reg(UInt(width = 64)) // regardless of XLEN
val reg_instret = WideCounter(64, io.retire)
val reg_cycle: UInt = if (enableCommitLog) { reg_instret } else { WideCounter(64) }
val mip = Wire(init=reg_mip)
mip.host := (reg_fromhost =/= 0)
mip.rocc := io.rocc.interrupt
@ -277,6 +278,20 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
read_mapping += CSRs.msinstret_delta -> UInt(0)
}
if (xLen == 32) {
read_mapping += CSRs.mtimeh -> (reg_time >> 32)
read_mapping += CSRs.mcycleh -> (reg_cycle >> 32)
read_mapping += CSRs.minstreth -> (reg_instret >> 32)
read_mapping += CSRs.mutime_deltah -> UInt(0)
read_mapping += CSRs.mucycle_deltah -> UInt(0)
read_mapping += CSRs.muinstret_deltah -> UInt(0)
if (usingVM) {
read_mapping += CSRs.mstime_deltah -> UInt(0)
read_mapping += CSRs.mscycle_deltah -> UInt(0)
read_mapping += CSRs.msinstret_deltah -> UInt(0)
}
}
for (i <- 0 until nCustomMrwCsrs) {
val addr = 0xff0 + i
require(addr < (1 << CSR.ADDRSZ))