riscv/rocket-chip
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ahb: make MMIO channels specifiy bus type (we will have more than one bridge)

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Wesley W. Terpstra 2016-05-26 14:14:56 -07:00 committed by Andrew Waterman
parent f3a557b67b
commit 7a24527448
2 changed files with 5 additions and 5 deletions
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2
src/main/scala/Configs.scala
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@ -218,7 +218,7 @@ class BaseConfig extends Config (
true true
} }
case NExtInterrupts => 2 case NExtInterrupts => 2
case NExtMMIOChannels => 0 case NExtMMIOAXIChannels => 0
case PLICKey => PLICConfig(site(NTiles), site(UseVM), site(NExtInterrupts), 0) case PLICKey => PLICConfig(site(NTiles), site(UseVM), site(NExtInterrupts), 0)
case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen)) case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen))
case FDivSqrt => true case FDivSqrt => true

8
src/main/scala/RocketChip.scala
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@ -20,7 +20,7 @@ case object BankIdLSB extends Field[Int]
/** Number of outstanding memory requests */ /** Number of outstanding memory requests */
case object NOutstandingMemReqsPerChannel extends Field[Int] case object NOutstandingMemReqsPerChannel extends Field[Int]
/** Number of exteral MMIO ports */ /** Number of exteral MMIO ports */
case object NExtMMIOChannels extends Field[Int] case object NExtMMIOAXIChannels extends Field[Int]
/** Whether to divide HTIF clock */ /** Whether to divide HTIF clock */
case object UseHtifClockDiv extends Field[Boolean] case object UseHtifClockDiv extends Field[Boolean]
/** Function for building some kind of coherence manager agent */ /** Function for building some kind of coherence manager agent */
@ -80,7 +80,7 @@ class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
class TopIO(implicit p: Parameters) extends BasicTopIO()(p) { class TopIO(implicit p: Parameters) extends BasicTopIO()(p) {
val mem = Vec(nMemChannels, new NastiIO) val mem = Vec(nMemChannels, new NastiIO)
val interrupts = Vec(p(NExtInterrupts), Bool()).asInput val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
val mmio = Vec(p(NExtMMIOChannels), new NastiIO) val mmio = Vec(p(NExtMMIOAXIChannels), new NastiIO)
val debug = new DebugBusIO()(p).flip val debug = new DebugBusIO()(p).flip
} }
@ -161,7 +161,7 @@ class Uncore(implicit val p: Parameters) extends Module
val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
val prci = Vec(nTiles, new PRCITileIO).asOutput val prci = Vec(nTiles, new PRCITileIO).asOutput
val mmio = Vec(p(NExtMMIOChannels), new NastiIO) val mmio = Vec(p(NExtMMIOAXIChannels), new NastiIO)
val interrupts = Vec(p(NExtInterrupts), Bool()).asInput val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
val debugBus = new DebugBusIO()(p).flip val debugBus = new DebugBusIO()(p).flip
} }
@ -228,7 +228,7 @@ class Uncore(implicit val p: Parameters) extends Module
val bootROM = Module(new ROMSlave(TopUtils.makeBootROM())) val bootROM = Module(new ROMSlave(TopUtils.makeBootROM()))
bootROM.io <> mmioNetwork.port("int:bootrom") bootROM.io <> mmioNetwork.port("int:bootrom")
val mmioEndpoint = p(NExtMMIOChannels) match { val mmioEndpoint = p(NExtMMIOAXIChannels) match {
case 0 => Module(new NastiErrorSlave).io case 0 => Module(new NastiErrorSlave).io
case 1 => io.mmio(0) case 1 => io.mmio(0)
// The memory map presently has only one external I/O region // The memory map presently has only one external I/O region