riscv/rocket-chip
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rocketchip: include an ErrorSlave by default

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This commit is contained in:
Wesley W. Terpstra 2017-04-20 12:09:02 -07:00
parent 641a4d577a
commit 7a1d107c9e
3 changed files with 31 additions and 1 deletions
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1
src/main/scala/rocketchip/Configs.scala
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@ -39,6 +39,7 @@ class BasePlatformConfig extends Config((site, here, up) => {
case IncludeJtagDTM => false
case JtagDTMKey => new JtagDTMKeyDefault()
case ZeroConfig => ZeroConfig(base=0xa000000L, size=0x2000000L, beatBytes=8)
case ErrorConfig => ErrorConfig(Seq(AddressSet(0x1000, 0xfff)))
case ExtMem => MasterConfig(base=0x80000000L, size=0x10000000L, beatBytes=8, idBits=4)
case ExtBus => MasterConfig(base=0x60000000L, size=0x20000000L, beatBytes=8, idBits=4)
case ExtIn => SlaveConfig(beatBytes=8, idBits=8, sourceBits=2)

3
src/main/scala/rocketchip/ExampleTop.scala
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@ -10,6 +10,7 @@ import rocketchip._
/** Example Top with Periphery (w/o coreplex) */
abstract class ExampleTop(implicit p: Parameters) extends BaseTop
with PeripheryAsyncExtInterrupts
with PeripheryErrorSlave
with PeripheryMasterAXI4Mem
with PeripheryMasterAXI4MMIO
with PeripherySlaveAXI4 {
@ -18,12 +19,14 @@ abstract class ExampleTop(implicit p: Parameters) extends BaseTop
class ExampleTopBundle[+L <: ExampleTop](_outer: L) extends BaseTopBundle(_outer)
with PeripheryExtInterruptsBundle
with PeripheryErrorSlaveBundle
with PeripheryMasterAXI4MemBundle
with PeripheryMasterAXI4MMIOBundle
with PeripherySlaveAXI4Bundle
class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io)
with PeripheryExtInterruptsModule
with PeripheryErrorSlaveModule
with PeripheryMasterAXI4MemModule
with PeripheryMasterAXI4MMIOModule
with PeripherySlaveAXI4Module

28
src/main/scala/rocketchip/Periphery.scala
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@ -13,7 +13,7 @@ import uncore.converters._
import uncore.devices._
import uncore.util._
import util._
import scala.math.max
import scala.math.{min,max}
/** Specifies the size of external memory */
case class MasterConfig(base: Long, size: Long, beatBytes: Int, idBits: Int)
@ -33,6 +33,9 @@ case object SOCBusConfig extends Field[TLBusConfig]
/* Specifies the location of the Zero device */
case class ZeroConfig(base: Long, size: Long, beatBytes: Int)
case object ZeroConfig extends Field[ZeroConfig]
/* Specifies the location of the Error device */
case class ErrorConfig(address: Seq[AddressSet])
case object ErrorConfig extends Field[ErrorConfig]
/** Utility trait for quick access to some relevant parameters */
trait HasPeripheryParameters {
@ -388,3 +391,26 @@ trait PeripheryTestBusMasterModule {
val io: PeripheryTestBusMasterBundle
} =>
}
/////
trait PeripheryErrorSlave {
this: HasTopLevelNetworks =>
private val config = p(ErrorConfig)
private val maxXfer = min(config.address.map(_.alignment).max.toInt, 4096)
val error = LazyModule(new TLError(config.address, peripheryBusConfig.beatBytes))
error.node := TLFragmenter(peripheryBusConfig.beatBytes, maxXfer)(peripheryBus.node)
}
trait PeripheryErrorSlaveBundle {
this: HasTopLevelNetworksBundle {
val outer: PeripheryErrorSlave
} =>
}
trait PeripheryErrorSlaveModule {
this: HasTopLevelNetworksModule {
val outer: PeripheryErrorSlave
val io: PeripheryErrorSlaveBundle
} =>
}