riscv/rocket-chip
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rocketchip: include an ErrorSlave by default

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This commit is contained in:
Wesley W. Terpstra
2017-04-20 12:09:02 -07:00
parent 641a4d577a
commit 7a1d107c9e
3 changed files with 31 additions and 1 deletions
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3
src/main/scala/rocketchip/ExampleTop.scala
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@ -10,6 +10,7 @@ import rocketchip._
/** Example Top with Periphery (w/o coreplex) */
abstract class ExampleTop(implicit p: Parameters) extends BaseTop
with PeripheryAsyncExtInterrupts
with PeripheryErrorSlave
with PeripheryMasterAXI4Mem
with PeripheryMasterAXI4MMIO
with PeripherySlaveAXI4 {
@ -18,12 +19,14 @@ abstract class ExampleTop(implicit p: Parameters) extends BaseTop
class ExampleTopBundle[+L <: ExampleTop](_outer: L) extends BaseTopBundle(_outer)
with PeripheryExtInterruptsBundle
with PeripheryErrorSlaveBundle
with PeripheryMasterAXI4MemBundle
with PeripheryMasterAXI4MMIOBundle
with PeripherySlaveAXI4Bundle
class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io)
with PeripheryExtInterruptsModule
with PeripheryErrorSlaveModule
with PeripheryMasterAXI4MemModule
with PeripheryMasterAXI4MMIOModule
with PeripherySlaveAXI4Module