riscv/rocket-chip
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Add some covers for FPU structural hazards

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This commit is contained in:
Andrew Waterman 2018-01-23 16:27:46 -08:00
parent a2ca82f92c
commit 7a0252fdfc
1 changed files with 9 additions and 0 deletions
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9
src/main/scala/tile/FPU.scala
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@ -10,6 +10,8 @@ import freechips.rocketchip.config.Parameters
import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.util._ import freechips.rocketchip.util._
import freechips.rocketchip.util.property._
import chisel3.internal.sourceinfo.SourceInfo
case class FPUParams( case class FPUParams(
divSqrt: Boolean = true, divSqrt: Boolean = true,
@ -768,6 +770,7 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint) val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)
ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback")
for (i <- 0 until maxLatency-2) { for (i <- 0 until maxLatency-2) {
when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }
@ -825,6 +828,9 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
if (cfg.divSqrt) { if (cfg.divSqrt) {
val divSqrt_killed = Reg(Bool()) val divSqrt_killed = Reg(Bool())
ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider")
ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard")
ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback")
for (t <- floatTypes) { for (t <- floatTypes) {
val tag = !mem_ctrl.singleOut // TODO typeTag val tag = !mem_ctrl.singleOut // TODO typeTag
@ -873,4 +879,7 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
} }
req req
} }
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
cover(cond, s"FPU_$label", "Core;;" + desc)
} }