riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

fix number of IOMSHRs at 1

Browse Source
This commit is contained in:
Howard Mao
2016-01-25 13:23:11 -08:00
parent 305185c034
commit 7937fbf074
1 changed files with 1 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
rocket/src/main/scala/nbdcache.scala
View File

@@ -12,7 +12,6 @@ case object WordBits extends Field[Int]
case object StoreDataQueueDepth extends Field[Int] case object StoreDataQueueDepth extends Field[Int]
case object ReplayQueueDepth extends Field[Int] case object ReplayQueueDepth extends Field[Int]
case object NMSHRs extends Field[Int] case object NMSHRs extends Field[Int]
case object NIOMSHRs extends Field[Int]
case object LRSCCycles extends Field[Int] case object LRSCCycles extends Field[Int]
trait HasL1HellaCacheParameters extends HasL1CacheParameters { trait HasL1HellaCacheParameters extends HasL1CacheParameters {
@@ -32,7 +31,7 @@ trait HasL1HellaCacheParameters extends HasL1CacheParameters {
val encRowBits = encDataBits*rowWords val encRowBits = encDataBits*rowWords
val sdqDepth = p(StoreDataQueueDepth) val sdqDepth = p(StoreDataQueueDepth)
val nMSHRs = p(NMSHRs) val nMSHRs = p(NMSHRs)
val nIOMSHRs = p(NIOMSHRs) val nIOMSHRs = 1
val lrscCycles = p(LRSCCycles) val lrscCycles = p(LRSCCycles)
} }