From f483bab4aaeff5186ef064d0cf972a874b7dac87 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 3 Aug 2017 00:52:12 -0700 Subject: [PATCH] Fix I$ miss perfctr The old version was counting prefetches, too. --- src/main/scala/rocket/Frontend.scala | 2 +- src/main/scala/rocket/ICache.scala | 8 ++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/main/scala/rocket/Frontend.scala b/src/main/scala/rocket/Frontend.scala index 597c713e..b4f873a9 100644 --- a/src/main/scala/rocket/Frontend.scala +++ b/src/main/scala/rocket/Frontend.scala @@ -285,7 +285,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer) io.cpu.resp <> fq.io.deq // performance events - io.cpu.perf.acquire := edge.done(icache.io.tl_out(0).a) + io.cpu.perf := icache.io.perf io.cpu.perf.tlbMiss := io.ptw.req.fire() def alignPC(pc: UInt) = ~(~pc | (coreInstBytes - 1)) diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index 00034e1e..d41321aa 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -68,6 +68,10 @@ class ICacheResp(outer: ICache) extends Bundle { override def cloneType = new ICacheResp(outer).asInstanceOf[this.type] } +class ICachePerfEvents extends Bundle { + val acquire = Bool() +} + class ICacheBundle(outer: ICache) extends CoreBundle()(outer.p) { val hartid = UInt(INPUT, hartIdLen) val req = Decoupled(new ICacheReq).flip @@ -81,6 +85,8 @@ class ICacheBundle(outer: ICache) extends CoreBundle()(outer.p) { val invalidate = Bool(INPUT) val tl_out = outer.masterNode.bundleOut val tl_in = outer.slaveNode.map(_.bundleIn) + + val perf = new ICachePerfEvents().asOutput } // get a tile-specific property without breaking deduplication @@ -343,4 +349,6 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) when (!refill_valid) { invalidated := false.B } when (refill_fire) { refill_valid := true.B } when (refill_done) { refill_valid := false.B} + + io.perf.acquire := refill_fire }