riscv/rocket-chip
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Don't report to the DTIM that data is cacheable

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Otherwise, it will attempt to perform AMOs where they're unsupported!
This commit is contained in:
Andrew Waterman 2017-08-08 11:55:04 -07:00
parent 74d309c18e
commit 7935c61c19
2 changed files with 2 additions and 2 deletions
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2
src/main/scala/rocket/DCache.scala
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@ -200,7 +200,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
when (s1_valid_not_nacked || s1_flush_valid) {
s2_req := s1_req
s2_req.addr := s1_paddr
s2_uncached := !tlb.io.resp.cacheable || Bool(usingDataScratchpad)
s2_uncached := !tlb.io.resp.cacheable
}
val s2_read = isRead(s2_req.cmd)
val s2_write = isWrite(s2_req.cmd)

2
src/main/scala/rocket/TLB.scala
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@ -113,7 +113,7 @@ class TLB(instruction: Boolean, lgMaxSize: Int, nEntries: Int)(implicit edge: TL
val legal_address = edge.manager.findSafe(mpu_physaddr).reduce(_||_)
def fastCheck(member: TLManagerParameters => Boolean) =
legal_address && edge.manager.fastProperty(mpu_physaddr, member, (b:Boolean) => Bool(b))
val cacheable = fastCheck(_.supportsAcquireB)
val cacheable = fastCheck(_.supportsAcquireB) && (instruction || !usingDataScratchpad)
val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits)(mpu_physaddr).homogeneous
val prot_r = fastCheck(_.supportsGet) && pmp.io.r
val prot_w = fastCheck(_.supportsPutFull) && pmp.io.w