From 79293f4fa295f3c89525140acb65f1b2baf23f26 Mon Sep 17 00:00:00 2001 From: Ben Keller Date: Thu, 25 Aug 2016 15:49:44 -0700 Subject: [PATCH] Use a better iterator inside the DCache --- src/main/scala/rocket/nbdcache.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/rocket/nbdcache.scala b/src/main/scala/rocket/nbdcache.scala index bcc8efd3..e490c549 100644 --- a/src/main/scala/rocket/nbdcache.scala +++ b/src/main/scala/rocket/nbdcache.scala @@ -755,13 +755,13 @@ class DataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) { val rway_en = io.read.bits.way_en(w+rowWords-1,w) val resp = Wire(Vec(rowWords, Bits(width = encRowBits))) val r_raddr = RegEnable(io.read.bits.addr, io.read.valid) - for (p <- 0 until resp.size) { + for (i <- 0 until resp.size) { val array = SeqMem(nSets*refillCycles, Vec(rowWords, Bits(width=encDataBits))) - when (wway_en.orR && io.write.valid && io.write.bits.wmask(p)) { - val data = Vec.fill(rowWords)(io.write.bits.data(encDataBits*(p+1)-1,encDataBits*p)) + when (wway_en.orR && io.write.valid && io.write.bits.wmask(i)) { + val data = Vec.fill(rowWords)(io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i)) array.write(waddr, data, wway_en.toBools) } - resp(p) := array.read(raddr, rway_en.orR && io.read.valid).asUInt + resp(i) := array.read(raddr, rway_en.orR && io.read.valid).asUInt } for (dw <- 0 until rowWords) { val r = Vec(resp.map(_(encDataBits*(dw+1)-1,encDataBits*dw)))