riscv/rocket-chip
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Chisel3 compatibility fixes

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This commit is contained in:
Andrew Waterman
2015-09-11 15:43:07 -07:00
parent 1718333f83
commit 78b2e947de
8 changed files with 23 additions and 25 deletions
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2
rocket/src/main/scala/arbiter.scala
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@@ -8,7 +8,7 @@ import uncore._
class HellaCacheArbiter(n: Int) extends Module
{
val io = new Bundle {
val requestor = Vec.fill(n){new HellaCacheIO}.flip
val requestor = Vec(new HellaCacheIO, n).flip
val mem = new HellaCacheIO
}

2
rocket/src/main/scala/btb.scala
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@@ -35,7 +35,7 @@ class RAS(nras: Int) {
private val count = Reg(init=UInt(0,log2Up(nras+1)))
private val pos = Reg(init=UInt(0,log2Up(nras)))
private val stack = Reg(Vec.fill(nras){UInt()})
private val stack = Reg(Vec(UInt(), nras))
}
class BHTResp extends Bundle with BTBParameters {

4
rocket/src/main/scala/csr.scala
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@@ -85,8 +85,8 @@ class CSRFileIO extends CoreBundle {
val evec = UInt(OUTPUT, vaddrBitsExtended)
val exception = Bool(INPUT)
val retire = UInt(INPUT, log2Up(1+retireWidth))
val uarch_counters = Vec.fill(16)(UInt(INPUT, log2Up(1+retireWidth)))
val custom_mrw_csrs = Vec.fill(params(NCustomMRWCSRs))(UInt(INPUT, xLen))
val uarch_counters = Vec(UInt(INPUT, log2Up(1+retireWidth)), 16)
val custom_mrw_csrs = Vec(UInt(INPUT, xLen), params(NCustomMRWCSRs))
val cause = UInt(INPUT, xLen)
val pc = UInt(INPUT, vaddrBitsExtended)
val fatc = Bool(OUTPUT)

2
rocket/src/main/scala/fpu.scala
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@@ -456,7 +456,7 @@ class FPU extends Module
val memLatencyMask = latencyMask(mem_ctrl, 2)
val wen = Reg(init=Bits(0, maxLatency-1))
val winfo = Reg(Vec.fill(maxLatency-1){Bits()})
val winfo = Reg(Vec(Bits(), maxLatency-1))
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, ex_reg_valid)
val mem_winfo = Cat(pipeid(mem_ctrl), mem_reg_inst(11,7))

9
rocket/src/main/scala/icache.scala
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@@ -21,7 +21,7 @@ class FrontendReq extends CoreBundle {
class FrontendResp extends CoreBundle {
val pc = UInt(width = vaddrBitsExtended) // ID stage PC
val data = Vec.fill(coreFetchWidth) (Bits(width = coreInstBits))
val data = Vec(Bits(width = coreInstBits), coreFetchWidth)
val mask = Bits(width = coreFetchWidth)
val xcpt_if = Bool()
}
@@ -196,12 +196,11 @@ class ICache extends FrontendModule
val repl_way = if (isDM) UInt(0) else LFSR16(s2_miss)(log2Up(nWays)-1,0)
val entagbits = code.width(tagBits)
val tag_array = SeqMem(Bits(width = entagbits*nWays), nSets)
val tag_array = SeqMem(Vec(Bits(width = entagbits), nWays), nSets)
val tag_rdata = tag_array.read(s0_pgoff(untagBits-1,blockOffBits), !refill_done && s0_valid)
when (refill_done) {
val wmask = FillInterleaved(entagbits, if (isDM) Bits(1) else UIntToOH(repl_way))
val tag = code.encode(s2_tag).toUInt
tag_array.write(s2_idx, Fill(nWays, tag), wmask)
tag_array.write(s2_idx, Vec.fill(nWays)(tag), Vec.tabulate(nWays)(repl_way === _))
}
val vb_array = Reg(init=Bits(0, nSets*nWays))
@@ -225,7 +224,7 @@ class ICache extends FrontendModule
val s2_vb = Reg(Bool())
val s2_tag_disparity = Reg(Bool())
val s2_tag_match = Reg(Bool())
val tag_out = tag_rdata(entagbits*(i+1)-1, entagbits*i)
val tag_out = tag_rdata(i)
when (s1_valid && rdy && !stall) {
s2_vb := s1_vb
s2_tag_disparity := code.decode(tag_out).error

21
rocket/src/main/scala/nbdcache.scala
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@@ -538,7 +538,7 @@ class DataArray extends L1HellaCacheModule {
val io = new Bundle {
val read = Decoupled(new L1DataReadReq).flip
val write = Decoupled(new L1DataWriteReq).flip
val resp = Vec.fill(nWays){Bits(OUTPUT, encRowBits)}
val resp = Vec(Bits(OUTPUT, encRowBits), nWays)
}
val waddr = io.write.bits.addr >> rowOffBits
@@ -551,13 +551,12 @@ class DataArray extends L1HellaCacheModule {
val resp = Wire(Vec(Bits(width = encRowBits), rowWords))
val r_raddr = RegEnable(io.read.bits.addr, io.read.valid)
for (p <- 0 until resp.size) {
val array = SeqMem(Bits(width=encRowBits), nSets*refillCycles)
val array = SeqMem(Vec(Bits(width=encDataBits), rowWords), nSets*refillCycles)
when (wway_en.orR && io.write.valid && io.write.bits.wmask(p)) {
val data = Fill(rowWords, io.write.bits.data(encDataBits*(p+1)-1,encDataBits*p))
val mask = FillInterleaved(encDataBits, wway_en)
array.write(waddr, data, mask)
val data = Vec.fill(rowWords)(io.write.bits.data(encDataBits*(p+1)-1,encDataBits*p))
array.write(waddr, data, wway_en.toBools)
}
resp(p) := array.read(raddr, rway_en.orR && io.read.valid)
resp(p) := array.read(raddr, rway_en.orR && io.read.valid).toBits
}
for (dw <- 0 until rowWords) {
val r = Vec(resp.map(_(encDataBits*(dw+1)-1,encDataBits*dw)))
@@ -568,13 +567,13 @@ class DataArray extends L1HellaCacheModule {
}
}
} else {
val wmask = FillInterleaved(encDataBits, io.write.bits.wmask)
for (w <- 0 until nWays) {
val array = SeqMem(Bits(width=encRowBits), nSets*refillCycles)
val array = SeqMem(Vec(Bits(width=encDataBits), rowWords), nSets*refillCycles)
when (io.write.bits.way_en(w) && io.write.valid) {
array.write(waddr, io.write.bits.data, wmask)
val data = Vec.tabulate(rowWords)(i => io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i))
array.write(waddr, data, io.write.bits.wmask.toBools)
}
io.resp(w) := array.read(raddr, io.read.bits.way_en(w) && io.read.valid)
io.resp(w) := array.read(raddr, io.read.bits.way_en(w) && io.read.valid).toBits
}
}
@@ -749,7 +748,7 @@ class HellaCache extends L1HellaCacheModule {
val s2_data = Wire(Vec(Bits(width=encRowBits), nWays))
for (w <- 0 until nWays) {
val regs = Reg(Vec.fill(rowWords){Bits(width = encDataBits)})
val regs = Reg(Vec(Bits(width = encDataBits), rowWords))
val en1 = s1_clk_en && s1_tag_eq_way(w)
for (i <- 0 until regs.size) {
val en = en1 && ((Bool(i == 0) || !Bool(doNarrowRead)) || s1_writeback)

2
rocket/src/main/scala/ptw.scala
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@@ -54,7 +54,7 @@ class PTE extends CoreBundle {
class PTW(n: Int) extends CoreModule
{
val io = new Bundle {
val requestor = Vec.fill(n){new TLBPTWIO}.flip
val requestor = Vec(new TLBPTWIO, n).flip
val mem = new HellaCacheIO
val dpath = new DatapathPTWIO
}

6
rocket/src/main/scala/rocket.scala
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@@ -180,9 +180,9 @@ class Rocket extends CoreModule
// execute stage
val bypass_mux = Vec(bypass_sources.map(_._3))
val ex_reg_rs_bypass = Reg(Vec.fill(id_raddr.size)(Bool()))
val ex_reg_rs_lsb = Reg(Vec.fill(id_raddr.size)(Bits()))
val ex_reg_rs_msb = Reg(Vec.fill(id_raddr.size)(Bits()))
val ex_reg_rs_bypass = Reg(Vec(Bool(), id_raddr.size))
val ex_reg_rs_lsb = Reg(Vec(UInt(), id_raddr.size))
val ex_reg_rs_msb = Reg(Vec(UInt(), id_raddr.size))
val ex_rs = for (i <- 0 until id_raddr.size)
yield Mux(ex_reg_rs_bypass(i), bypass_mux(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i)))
val ex_imm = imm(ex_ctrl.sel_imm, ex_reg_inst)