riscv/rocket-chip
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Chisel3 compatibility fixes

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This commit is contained in:
Andrew Waterman
2015-09-11 15:43:07 -07:00
parent 1718333f83
commit 78b2e947de
8 changed files with 23 additions and 25 deletions
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6
rocket/src/main/scala/rocket.scala
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@ -180,9 +180,9 @@ class Rocket extends CoreModule
// execute stage
val bypass_mux = Vec(bypass_sources.map(_._3))
val ex_reg_rs_bypass = Reg(Vec.fill(id_raddr.size)(Bool()))
val ex_reg_rs_lsb = Reg(Vec.fill(id_raddr.size)(Bits()))
val ex_reg_rs_msb = Reg(Vec.fill(id_raddr.size)(Bits()))
val ex_reg_rs_bypass = Reg(Vec(Bool(), id_raddr.size))
val ex_reg_rs_lsb = Reg(Vec(UInt(), id_raddr.size))
val ex_reg_rs_msb = Reg(Vec(UInt(), id_raddr.size))
val ex_rs = for (i <- 0 until id_raddr.size)
yield Mux(ex_reg_rs_bypass(i), bypass_mux(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i)))
val ex_imm = imm(ex_ctrl.sel_imm, ex_reg_inst)