Chisel3 compatibility fixes
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@ -54,7 +54,7 @@ class PTE extends CoreBundle {
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class PTW(n: Int) extends CoreModule
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{
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val io = new Bundle {
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val requestor = Vec.fill(n){new TLBPTWIO}.flip
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val requestor = Vec(new TLBPTWIO, n).flip
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val mem = new HellaCacheIO
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val dpath = new DatapathPTWIO
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}
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