riscv/rocket-chip
1
0 Fork 0
Code Releases Activity

Chisel3 compatibility fixes

Browse Source
This commit is contained in:
Andrew Waterman committed 2015-09-11 15:43:07 -07:00
1 parent 1718333f83
commit 78b2e947de
8 files changed
+23 -25
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

rocket/src/main/scala/csr.scala
+2 -2
View File
@@ -85,8 +85,8 @@ class CSRFileIO extends CoreBundle {
val evec = UInt(OUTPUT, vaddrBitsExtended)
val exception = Bool(INPUT)
val retire = UInt(INPUT, log2Up(1+retireWidth))
val uarch_counters = Vec.fill(16)(UInt(INPUT, log2Up(1+retireWidth)))
val custom_mrw_csrs = Vec.fill(params(NCustomMRWCSRs))(UInt(INPUT, xLen))
val uarch_counters = Vec(UInt(INPUT, log2Up(1+retireWidth)), 16)
val custom_mrw_csrs = Vec(UInt(INPUT, xLen), params(NCustomMRWCSRs))
val cause = UInt(INPUT, xLen)
val pc = UInt(INPUT, vaddrBitsExtended)
val fatc = Bool(OUTPUT)