riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Chisel3 compatibility fixes

Browse Source
This commit is contained in:
Andrew Waterman
2015-09-11 15:43:07 -07:00
parent 1718333f83
commit 78b2e947de
8 changed files with 23 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
rocket/src/main/scala/btb.scala
View File

@ -35,7 +35,7 @@ class RAS(nras: Int) {
private val count = Reg(init=UInt(0,log2Up(nras+1)))
private val pos = Reg(init=UInt(0,log2Up(nras)))
private val stack = Reg(Vec.fill(nras){UInt()})
private val stack = Reg(Vec(UInt(), nras))
}
class BHTResp extends Bundle with BTBParameters {