diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index e3fcbbac..5ba1b8b2 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -206,7 +206,7 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf
   htif.io.host.in.bits := hio.io.in_fast.bits
   hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htif_width), Bool(true), htif.io.host.in.ready)
   io.host.clk := hio.io.clk_slow
-  io.host.clk_edge := RegUpdate(io.host.clk && !RegUpdate(io.host.clk))
+  io.host.clk_edge := Reg(next=io.host.clk && !Reg(next=io.host.clk))
 }
 
 class TopIO(htifWidth: Int) extends Bundle  {
@@ -268,12 +268,12 @@ class Top extends Module {
     val tile = tileList(i)
     tile.io.tilelink <> tl
     il := hl.reset
-    tile.io.host.reset := RegUpdate(RegUpdate(hl.reset))
+    tile.io.host.reset := Reg(next=Reg(next=hl.reset))
     tile.io.host.pcr_req <> Queue(hl.pcr_req)
     hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
     hl.ipi_req <> Queue(tile.io.host.ipi_req)
     tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
-    error_mode = error_mode || RegUpdate(tile.io.host.debug.error_mode)
+    error_mode = error_mode || Reg(next=tile.io.host.debug.error_mode)
   }
 
   io.host <> uncore.io.host
diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala
index 50590da3..7844da14 100644
--- a/src/main/scala/fpga.scala
+++ b/src/main/scala/fpga.scala
@@ -113,7 +113,7 @@ class FPGATop extends Module {
 
     tile.io.tilelink <> tl
     il := hl.reset
-    tile.io.host.reset := RegUpdate(RegUpdate(hl.reset))
+    tile.io.host.reset := Reg(next=Reg(next=hl.reset))
     tile.io.host.pcr_req <> Queue(hl.pcr_req)
     hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
     hl.ipi_req <> Queue(tile.io.host.ipi_req)
@@ -176,8 +176,8 @@ class Slave extends AXISlave
   require(dw >= top.io.mem.req_cmd.bits.addr.getWidth + 1 + 1)
 
   // write cr1 -> mem.resp (nonblocking)
-  val in_count = RegReset(UInt(0, log2Up(memw/dw)))
-  val rf_count = RegReset(UInt(0, log2Up(REFILL_CYCLES)))
+  val in_count = Reg(init=UInt(0, log2Up(memw/dw)))
+  val rf_count = Reg(init=UInt(0, log2Up(REFILL_CYCLES)))
   require(memw % dw == 0 && isPow2(memw/dw))
   val in_reg = Reg(top.io.mem.resp.bits.data)
   top.io.mem.resp.bits.data := Cat(io.in.bits, in_reg(in_reg.getWidth-1,dw))
@@ -194,7 +194,7 @@ class Slave extends AXISlave
   }
 
   // read cr2 -> mem.req_data (blocking)
-  val out_count = RegReset(UInt(0, log2Up(memw/dw)))
+  val out_count = Reg(init=UInt(0, log2Up(memw/dw)))
   top.io.mem.req_data.ready := ren(2) && out_count.andR
   rdata(2) := top.io.mem.req_data.bits.data >> (out_count * UInt(dw))
   rvalid(2) := top.io.mem.req_data.valid
diff --git a/src/main/scala/network.scala b/src/main/scala/network.scala
index 5b20491f..3bc57b9e 100644
--- a/src/main/scala/network.scala
+++ b/src/main/scala/network.scala
@@ -40,7 +40,7 @@ class TileLinkHeaderAppender[T <: SourcedMessage with HasPhysicalAddress, U <: S
   } else {
     val meta_has_data = conf.co.messageHasData(meta_q.bits.payload)
     val addr_q = Module(new Queue(io.in.meta.bits.payload.addr.clone, 2, pipe = true, flow = true))
-    val data_cnt = RegReset(UInt(0, width = log2Up(REFILL_CYCLES)))
+    val data_cnt = Reg(init=UInt(0, width = log2Up(REFILL_CYCLES)))
     val data_cnt_up = data_cnt + UInt(1)
 
     io.out.meta.bits.payload := meta_q.bits.payload