riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Get rid of the unecessary Parameters for Async Reset Reg

Browse Source
This commit is contained in:
Megan Wachs 2016-09-09 16:24:35 -07:00
parent e6889ea711
commit 77e4aa63f8
1 changed files with 3 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/main/scala/uncore/util/BlackBoxRegs.scala
View File

@ -3,7 +3,6 @@ package uncore.util
import Chisel._ import Chisel._
import cde.{Parameters} import cde.{Parameters}
import junctions.{ParameterizedBundle}
/** This black-boxes an Async Reset /** This black-boxes an Async Reset
* Reg. * Reg.
@ -47,7 +46,7 @@ class AsyncResetReg extends BlackBox {
} }
class SimpleRegIO(val w: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p){ class SimpleRegIO(val w: Int) extends Bundle{
val d = UInt(INPUT, width = w) val d = UInt(INPUT, width = w)
val q = UInt(OUTPUT, width = w) val q = UInt(OUTPUT, width = w)
@ -56,9 +55,9 @@ class SimpleRegIO(val w: Int)(implicit val p: Parameters) extends ParameterizedB
} }
class AsyncResetRegVec(val w: Int, val init: Int)(implicit val p: Parameters) extends Module { class AsyncResetRegVec(val w: Int, val init: Int) extends Module {
val io = new SimpleRegIO(w)(p) val io = new SimpleRegIO(w)
val bb_q = Wire(UInt(width = w)) val bb_q = Wire(UInt(width = w))
val bb_d = Wire(UInt(width = w)) val bb_d = Wire(UInt(width = w))