From 778c8a5c9751f8c7262b710c8e2db286d2d9de7f Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Thu, 16 Mar 2017 15:17:05 -0700
Subject: [PATCH] ToAHB: appease AHB VIP

---
 src/main/scala/uncore/tilelink2/ToAHB.scala | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/main/scala/uncore/tilelink2/ToAHB.scala b/src/main/scala/uncore/tilelink2/ToAHB.scala
index cbf87d3a..e3ca09fd 100644
--- a/src/main/scala/uncore/tilelink2/ToAHB.scala
+++ b/src/main/scala/uncore/tilelink2/ToAHB.scala
@@ -68,6 +68,10 @@ class TLToAHB(val aFlow: Boolean = false)(implicit p: Parameters) extends LazyMo
       resetState.full  := Bool(false)
       resetState.send  := Bool(false)
       resetState.first := Bool(true)
+      // These are needed to appease AHB VIP:
+      resetState.hsize := UInt(0)
+      resetState.hburst:= UInt(0)
+      resetState.addr  := UInt(0)
 
       // The stages of the combinational pipeline
       val reg  = RegInit(resetState)