tilelink2 RegisterRouter: add RegField test patterns
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src/main/scala/uncore/tilelink2/RegisterRouterTest.scala
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142
src/main/scala/uncore/tilelink2/RegisterRouterTest.scala
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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object LFSR16Seed
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{
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def apply(seed: Int): UInt =
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{
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val width = 16
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val lfsr = Reg(init=UInt(seed, width))
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lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1))
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lfsr
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}
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}
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class RRTestCombinational(val bits: Int, rvalid: Bool => Bool, wready: Bool => Bool) extends Module
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{
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val io = new Bundle {
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val rvalid = Bool(OUTPUT)
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val rready = Bool(INPUT)
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val rdata = UInt(OUTPUT, width = bits)
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val wvalid = Bool(INPUT)
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val wready = Bool(OUTPUT)
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val wdata = UInt(INPUT, width = bits)
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}
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val rfire = io.rvalid && io.rready
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val wfire = io.wvalid && io.wready
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val reg = Reg(UInt(width = bits))
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io.rvalid := rvalid(rfire)
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io.wready := wready(wfire)
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io.rdata := Mux(rfire, reg, UInt(0))
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when (wfire) { reg := io.wdata }
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}
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object RRTestCombinational
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{
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private var seed = 0
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def always: Bool => Bool = _ => Bool(true)
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def random: Bool => Bool = {
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seed = seed + 1
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val lfsr = LFSR16Seed(seed)
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_ => lfsr(0)
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}
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def delay(x: Int): Bool => Bool = { fire =>
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val reg = RegInit(UInt(0, width = log2Ceil(x+1)))
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val ready = reg === UInt(0)
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reg := Mux(fire, UInt(x), Mux(ready, UInt(0), reg - UInt(1)))
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ready
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}
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def combo(bits: Int, rvalid: Bool => Bool, wready: Bool => Bool): RegField = {
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val combo = Module(new RRTestCombinational(bits, rvalid, wready))
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RegField(bits,
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RegReadFn { ready => combo.io.rready := ready; (combo.io.rvalid, combo.io.rdata) },
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RegWriteFn { (valid, data) => combo.io.wvalid := valid; combo.io.wdata := data; combo.io.wready })
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}
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}
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class RRTestRequest(val bits: Int,
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rflow: (Bool, Bool, UInt) => (Bool, Bool, UInt),
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wflow: (Bool, Bool, UInt) => (Bool, Bool, UInt)) extends Module
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{
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val io = new Bundle {
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val rivalid = Bool(INPUT)
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val riready = Bool(OUTPUT)
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val rovalid = Bool(OUTPUT)
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val roready = Bool(INPUT)
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val rdata = UInt(OUTPUT, width = bits)
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val wivalid = Bool(INPUT)
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val wiready = Bool(OUTPUT)
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val wovalid = Bool(OUTPUT)
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val woready = Bool(INPUT)
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val wdata = UInt(INPUT, width = bits)
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}
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val (riready, rovalid, _) = rflow(io.rivalid, io.roready, UInt(0, width = 1))
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val (wiready, wovalid, wdata) = wflow(io.wivalid, io.woready, io.wdata)
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val reg = Reg(UInt(width = bits))
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io.riready := riready
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io.rovalid := rovalid
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io.wiready := wiready
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io.wovalid := wovalid
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val rofire = io.roready && rovalid
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val wofire = io.woready && wovalid
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io.rdata := Mux(rofire, reg, UInt(0))
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when (wofire) { reg := wdata }
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}
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object RRTestRequest
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{
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private var seed = 0
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def pipe(x: Int): (Bool, Bool, UInt) => (Bool, Bool, UInt) = { (ivalid, oready, idata) =>
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val full = RegInit(Vec.fill(x)(Bool(false)))
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val ready = Wire(Vec.fill(x)(Bool()))
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val data = Reg(Vec.fill(x)(UInt(width = idata.getWidth)))
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// Construct a classic bubble-filling pipeline
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ready(x) := oready || !full(x)
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when (ready(0)) { data(0) := idata }
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((ready.init zip ready.tail) zip full.init) foreach { case ((self, next), full) =>
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self := next || !full
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}
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((data.init zip data.tail) zip ready.tail) foreach { case ((prev, self), ready) =>
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when (ready) { self := prev }
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}
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(ready(0), full(x), Mux(full(x) && oready, data(x), UInt(0)))
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}
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def busy: (Bool, Bool, UInt) => (Bool, Bool, UInt) = {
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seed = seed + 1
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val lfsr = LFSR16Seed(seed)
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(ivalid, oready, idata) => {
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val busy = RegInit(Bool(false))
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val progress = lfsr(0)
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when (progress) {
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busy := Mux(busy, !oready, ivalid)
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}
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(progress && !busy, progress && busy, idata)
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}
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}
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def request(bits: Int,
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rflow: (Bool, Bool, UInt) => (Bool, Bool, UInt),
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wflow: (Bool, Bool, UInt) => (Bool, Bool, UInt)): RegField = {
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val request = Module(new RRTestRequest(bits, rflow, wflow))
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RegField(bits,
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RegReadFn { (rivalid, roready) =>
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request.io.rivalid := rivalid
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request.io.roready := roready
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(request.io.riready, request.io.rovalid, request.io.rdata) },
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RegWriteFn { (wivalid, woready, wdata) =>
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request.io.wivalid := wivalid
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request.io.woready := woready
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request.io.wdata := wdata
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(request.io.wiready, request.io.wovalid) })
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}
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}
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