riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Make NastiMemorySelector a subtype of NastiInterconnect

Browse Source 
When RocketChip has a single memory configuration I want to ensure no extra
hardware is being generated by only instantiating a NastiMemoryInterconnect
rather than a NastiMemorySelector, which I believe will insert a Mux with 0
when there is only one config (because there aren't any 0-width wires allowed).
This commit is contained in:
Palmer Dabbelt
2016-02-17 10:41:01 -08:00
parent 6b39db8ce6
commit 770f2742de
1 changed files with 12 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
junctions/src/main/scala/nasti.scala
View File

@@ -602,16 +602,22 @@ class NastiMemoryInterconnect(
* this module violate Nasti, it also causes the memory of the machine to * this module violate Nasti, it also causes the memory of the machine to
* become garbled. It's expected that select only changes at boot time, as * become garbled. It's expected that select only changes at boot time, as
* part of the memory controller configuration. */ * part of the memory controller configuration. */
class NastiMemorySelector(nBanks: Int, maxMemChannels: Int, configs: Seq[Int])(implicit p: Parameters) extends NastiModule()(p) { class NastiMemorySelectorIO(val nBanks: Int, val maxMemChannels: Int, nConfigs: Int)
(implicit p: Parameters)
extends NastiInterconnectIO(nBanks, maxMemChannels) {
val select = UInt(INPUT, width = log2Up(nConfigs))
override def cloneType =
new NastiMemorySelectorIO(nMasters, nSlaves, nConfigs).asInstanceOf[this.type]
}
class NastiMemorySelector(nBanks: Int, maxMemChannels: Int, configs: Seq[Int])
(implicit p: Parameters)
extends NastiInterconnect()(p) {
val nMasters = nBanks val nMasters = nBanks
val nSlaves = maxMemChannels val nSlaves = maxMemChannels
val nConfigs = configs.size val nConfigs = configs.size
val io = new Bundle { override lazy val io = new NastiMemorySelectorIO(nBanks, maxMemChannels, nConfigs)
val masters = Vec(nMasters, new NastiIO).flip
val slaves = Vec(nSlaves, new NastiIO)
val select = UInt(INPUT, width = log2Up(nConfigs))
}
def muxOnSelect(up: DecoupledIO[Bundle], dn: DecoupledIO[Bundle], active: Bool): Unit = { def muxOnSelect(up: DecoupledIO[Bundle], dn: DecoupledIO[Bundle], active: Bool): Unit = {
when (active) { dn.bits := up.bits } when (active) { dn.bits := up.bits }