tilelink2: remove 'strided'; !contiguous is clearer

src/main/scala/rocketchip/Utils.scala

@@ -77,7 +77,7 @@ object GenerateGlobalAddrMap {
         (if (manager.executable)      AddrMapProt.X else 0), cacheable)
       val multi = manager.address.size > 1
       manager.address.zipWithIndex.map { case (address, i) =>
-        require (!address.strided) // TL1 can't do this
+        require (address.contiguous) // TL1 needs this
         val name = manager.name + (if (multi) ".%d".format(i) else "")
         AddrMapEntry(name, MemRange(address.base, address.mask+1, attr))
       }

src/main/scala/uncore/tilelink2/Parameters.scala

@@ -95,10 +95,8 @@ case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
 
   // The number of bytes to which the manager must be aligned
   def alignment = ((mask + 1) & ~mask)
-
   // Is this a contiguous memory range
   def contiguous = alignment == mask+1
-  def strided = alignment != mask+1
 
   def finite = mask >= 0
   def max = { require (finite); base | mask }
@@ -162,7 +160,7 @@ case class TLManagerParameters(
   lazy val dts = customDTS.getOrElse {
     val header = s"${name} {\n"
     val middle = address.map { a =>
-      require (!a.strided) // Config String does not support this
+      require (a.contiguous) // Config String is not so flexible
       "  addr 0x%x;\n  size 0x%x;\n".format(a.base, a.mask+1)
     }
     val footer = "}\n"

src/main/scala/uncore/tilelink2/RegisterRouter.scala

@@ -12,7 +12,7 @@ class TLRegisterNode(address: AddressSet, concurrency: Option[Int] = None, beatB
     supportsPutFull    = TransferSizes(1, beatBytes),
     fifoId             = Some(0))) // requests are handled in order
 {
-  require (!address.strided)
+  require (address.contiguous)
 
   // Calling this method causes the matching TL2 bundle to be
   // configured to route all requests to the listed RegFields.