riscv/rocket-chip
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tilelink2: remove 'strided'; !contiguous is clearer

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This commit is contained in:
Wesley W. Terpstra 2016-09-17 15:31:35 -07:00
parent fa0f119f3c
commit 76d8ed6a69
3 changed files with 3 additions and 5 deletions
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2
src/main/scala/rocketchip/Utils.scala
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@ -77,7 +77,7 @@ object GenerateGlobalAddrMap {
(if (manager.executable) AddrMapProt.X else 0), cacheable) (if (manager.executable) AddrMapProt.X else 0), cacheable)
val multi = manager.address.size > 1 val multi = manager.address.size > 1
manager.address.zipWithIndex.map { case (address, i) => manager.address.zipWithIndex.map { case (address, i) =>
require (!address.strided) // TL1 can't do this require (address.contiguous) // TL1 needs this
val name = manager.name + (if (multi) ".%d".format(i) else "") val name = manager.name + (if (multi) ".%d".format(i) else "")
AddrMapEntry(name, MemRange(address.base, address.mask+1, attr)) AddrMapEntry(name, MemRange(address.base, address.mask+1, attr))
} }

4
src/main/scala/uncore/tilelink2/Parameters.scala
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@ -95,10 +95,8 @@ case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
// The number of bytes to which the manager must be aligned // The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask) def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range // Is this a contiguous memory range
def contiguous = alignment == mask+1 def contiguous = alignment == mask+1
def strided = alignment != mask+1
def finite = mask >= 0 def finite = mask >= 0
def max = { require (finite); base | mask } def max = { require (finite); base | mask }
@ -162,7 +160,7 @@ case class TLManagerParameters(
lazy val dts = customDTS.getOrElse { lazy val dts = customDTS.getOrElse {
val header = s"${name} {\n" val header = s"${name} {\n"
val middle = address.map { a => val middle = address.map { a =>
require (!a.strided) // Config String does not support this require (a.contiguous) // Config String is not so flexible
" addr 0x%x;\n size 0x%x;\n".format(a.base, a.mask+1) " addr 0x%x;\n size 0x%x;\n".format(a.base, a.mask+1)
} }
val footer = "}\n" val footer = "}\n"

2
src/main/scala/uncore/tilelink2/RegisterRouter.scala
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@ -12,7 +12,7 @@ class TLRegisterNode(address: AddressSet, concurrency: Option[Int] = None, beatB
supportsPutFull = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes),
fifoId = Some(0))) // requests are handled in order fifoId = Some(0))) // requests are handled in order
{ {
require (!address.strided) require (address.contiguous)
// Calling this method causes the matching TL2 bundle to be // Calling this method causes the matching TL2 bundle to be
// configured to route all requests to the listed RegFields. // configured to route all requests to the listed RegFields.