From 76c2aa16613312d82337c35fef91ebc005cd3a90 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Tue, 26 Sep 2017 12:28:59 -0700 Subject: [PATCH] diplomacy: introduce the typing-saving SimpleNodeImp --- src/main/scala/amba/ahb/Nodes.scala | 12 ++++-------- src/main/scala/amba/apb/Nodes.scala | 12 ++++-------- src/main/scala/amba/axi4/Nodes.scala | 12 ++++-------- src/main/scala/diplomacy/Nodes.scala | 15 +++++++++++++++ src/main/scala/tilelink/IntNodes.scala | 11 ++++------- src/main/scala/tilelink/Nodes.scala | 21 +++++++-------------- 6 files changed, 38 insertions(+), 45 deletions(-) diff --git a/src/main/scala/amba/ahb/Nodes.scala b/src/main/scala/amba/ahb/Nodes.scala index 5d2f2bb8..16a2c884 100644 --- a/src/main/scala/amba/ahb/Nodes.scala +++ b/src/main/scala/amba/ahb/Nodes.scala @@ -7,17 +7,13 @@ import chisel3.internal.sourceinfo.SourceInfo import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ -object AHBImp extends NodeImp[AHBMasterPortParameters, AHBSlavePortParameters, AHBEdgeParameters, AHBEdgeParameters, AHBBundle] +object AHBImp extends SimpleNodeImp[AHBMasterPortParameters, AHBSlavePortParameters, AHBEdgeParameters, AHBBundle] { - def edgeO(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters, p: Parameters, sourceInfo: SourceInfo): AHBEdgeParameters = AHBEdgeParameters(pd, pu, p, sourceInfo) - def edgeI(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters, p: Parameters, sourceInfo: SourceInfo): AHBEdgeParameters = AHBEdgeParameters(pd, pu, p, sourceInfo) - - def bundleO(eo: AHBEdgeParameters): AHBBundle = AHBBundle(eo.bundle) - def bundleI(ei: AHBEdgeParameters): AHBBundle = AHBBundle(ei.bundle) + def edge(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters, p: Parameters, sourceInfo: SourceInfo): AHBEdgeParameters = AHBEdgeParameters(pd, pu, p, sourceInfo) + def bundle(e: AHBEdgeParameters): AHBBundle = AHBBundle(e.bundle) def colour = "#00ccff" // bluish - override def labelI(ei: AHBEdgeParameters) = (ei.slave.beatBytes * 8).toString - override def labelO(eo: AHBEdgeParameters) = (eo.slave.beatBytes * 8).toString + override def label(e: AHBEdgeParameters) = (e.slave.beatBytes * 8).toString override def mixO(pd: AHBMasterPortParameters, node: OutwardNode[AHBMasterPortParameters, AHBSlavePortParameters, AHBBundle]): AHBMasterPortParameters = pd.copy(masters = pd.masters.map { c => c.copy (nodePath = node +: c.nodePath) }) diff --git a/src/main/scala/amba/apb/Nodes.scala b/src/main/scala/amba/apb/Nodes.scala index 59acd587..117b3529 100644 --- a/src/main/scala/amba/apb/Nodes.scala +++ b/src/main/scala/amba/apb/Nodes.scala @@ -7,17 +7,13 @@ import chisel3.internal.sourceinfo.SourceInfo import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ -object APBImp extends NodeImp[APBMasterPortParameters, APBSlavePortParameters, APBEdgeParameters, APBEdgeParameters, APBBundle] +object APBImp extends SimpleNodeImp[APBMasterPortParameters, APBSlavePortParameters, APBEdgeParameters, APBBundle] { - def edgeO(pd: APBMasterPortParameters, pu: APBSlavePortParameters, p: Parameters, sourceInfo: SourceInfo): APBEdgeParameters = APBEdgeParameters(pd, pu, p, sourceInfo) - def edgeI(pd: APBMasterPortParameters, pu: APBSlavePortParameters, p: Parameters, sourceInfo: SourceInfo): APBEdgeParameters = APBEdgeParameters(pd, pu, p, sourceInfo) - - def bundleO(eo: APBEdgeParameters): APBBundle = APBBundle(eo.bundle) - def bundleI(ei: APBEdgeParameters): APBBundle = APBBundle(ei.bundle) + def edge(pd: APBMasterPortParameters, pu: APBSlavePortParameters, p: Parameters, sourceInfo: SourceInfo): APBEdgeParameters = APBEdgeParameters(pd, pu, p, sourceInfo) + def bundle(e: APBEdgeParameters): APBBundle = APBBundle(e.bundle) def colour = "#00ccff" // bluish - override def labelI(ei: APBEdgeParameters) = (ei.slave.beatBytes * 8).toString - override def labelO(eo: APBEdgeParameters) = (eo.slave.beatBytes * 8).toString + override def label(e: APBEdgeParameters) = (e.slave.beatBytes * 8).toString override def mixO(pd: APBMasterPortParameters, node: OutwardNode[APBMasterPortParameters, APBSlavePortParameters, APBBundle]): APBMasterPortParameters = pd.copy(masters = pd.masters.map { c => c.copy (nodePath = node +: c.nodePath) }) diff --git a/src/main/scala/amba/axi4/Nodes.scala b/src/main/scala/amba/axi4/Nodes.scala index 89d9fce8..683981e4 100644 --- a/src/main/scala/amba/axi4/Nodes.scala +++ b/src/main/scala/amba/axi4/Nodes.scala @@ -7,17 +7,13 @@ import chisel3.internal.sourceinfo.SourceInfo import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ -object AXI4Imp extends NodeImp[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4EdgeParameters, AXI4EdgeParameters, AXI4Bundle] +object AXI4Imp extends SimpleNodeImp[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4EdgeParameters, AXI4Bundle] { - def edgeO(pd: AXI4MasterPortParameters, pu: AXI4SlavePortParameters, p: Parameters, sourceInfo: SourceInfo): AXI4EdgeParameters = AXI4EdgeParameters(pd, pu, p, sourceInfo) - def edgeI(pd: AXI4MasterPortParameters, pu: AXI4SlavePortParameters, p: Parameters, sourceInfo: SourceInfo): AXI4EdgeParameters = AXI4EdgeParameters(pd, pu, p, sourceInfo) - - def bundleO(eo: AXI4EdgeParameters): AXI4Bundle = AXI4Bundle(eo.bundle) - def bundleI(ei: AXI4EdgeParameters): AXI4Bundle = AXI4Bundle(ei.bundle) + def edge(pd: AXI4MasterPortParameters, pu: AXI4SlavePortParameters, p: Parameters, sourceInfo: SourceInfo): AXI4EdgeParameters = AXI4EdgeParameters(pd, pu, p, sourceInfo) + def bundle(e: AXI4EdgeParameters): AXI4Bundle = AXI4Bundle(e.bundle) def colour = "#00ccff" // bluish - override def labelI(ei: AXI4EdgeParameters) = (ei.slave.beatBytes * 8).toString - override def labelO(eo: AXI4EdgeParameters) = (eo.slave.beatBytes * 8).toString + override def label(e: AXI4EdgeParameters) = (e.slave.beatBytes * 8).toString override def mixO(pd: AXI4MasterPortParameters, node: OutwardNode[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle]): AXI4MasterPortParameters = pd.copy(masters = pd.masters.map { c => c.copy (nodePath = node +: c.nodePath) }) diff --git a/src/main/scala/diplomacy/Nodes.scala b/src/main/scala/diplomacy/Nodes.scala index 0afd9830..3d4263d1 100644 --- a/src/main/scala/diplomacy/Nodes.scala +++ b/src/main/scala/diplomacy/Nodes.scala @@ -65,6 +65,21 @@ trait OutwardNodeImp[DO, UO, EO, BO <: Data] abstract class NodeImp[D, U, EO, EI, B <: Data] extends Object with InwardNodeImp[D, U, EI, B] with OutwardNodeImp[D, U, EO, B] +// If your edges have the same direction, using this saves you some typing +abstract class SimpleNodeImp[D, U, E, B <: Data] + extends NodeImp[D, U, E, E, B] +{ + def edge(pd: D, pu: U, p: Parameters, sourceInfo: SourceInfo): E + def edgeO(pd: D, pu: U, p: Parameters, sourceInfo: SourceInfo) = edge(pd, pu, p, sourceInfo) + def edgeI(pd: D, pu: U, p: Parameters, sourceInfo: SourceInfo) = edge(pd, pu, p, sourceInfo) + def bundle(e: E): B + def bundleO(e: E) = bundle(e) + def bundleI(e: E) = bundle(e) + def label(e: E): String = "" + override def labelO(e: E) = label(e) + override def labelI(e: E) = label(e) +} + abstract class BaseNode(implicit val valName: ValName) { require (!LazyModule.stack.isEmpty, "You cannot create a node outside a LazyModule!") diff --git a/src/main/scala/tilelink/IntNodes.scala b/src/main/scala/tilelink/IntNodes.scala index c0339b77..60b186dc 100644 --- a/src/main/scala/tilelink/IntNodes.scala +++ b/src/main/scala/tilelink/IntNodes.scala @@ -63,17 +63,14 @@ object IntSinkPortSimple case class IntEdge(source: IntSourcePortParameters, sink: IntSinkPortParameters, params: Parameters, sourceInfo: SourceInfo) -object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, IntEdge, IntEdge, Vec[Bool]] +object IntImp extends SimpleNodeImp[IntSourcePortParameters, IntSinkPortParameters, IntEdge, Vec[Bool]] { - def edgeO(pd: IntSourcePortParameters, pu: IntSinkPortParameters, p: Parameters, sourceInfo: SourceInfo): IntEdge = IntEdge(pd, pu, p, sourceInfo) - def edgeI(pd: IntSourcePortParameters, pu: IntSinkPortParameters, p: Parameters, sourceInfo: SourceInfo): IntEdge = IntEdge(pd, pu, p, sourceInfo) - def bundleO(eo: IntEdge): Vec[Bool] = Vec(eo.source.num, Bool()) - def bundleI(ei: IntEdge): Vec[Bool] = Vec(ei.source.num, Bool()) + def edge(pd: IntSourcePortParameters, pu: IntSinkPortParameters, p: Parameters, sourceInfo: SourceInfo): IntEdge = IntEdge(pd, pu, p, sourceInfo) + def bundle(e: IntEdge): Vec[Bool] = Vec(e.source.num, Bool()) def colour = "#0000ff" // blue override def reverse = true - override def labelI(ei: IntEdge) = ei.source.sources.map(_.range.size).sum.toString - override def labelO(eo: IntEdge) = eo.source.sources.map(_.range.size).sum.toString + override def label(e: IntEdge) = e.source.sources.map(_.range.size).sum.toString override def mixO(pd: IntSourcePortParameters, node: OutwardNode[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]): IntSourcePortParameters = pd.copy(sources = pd.sources.map { s => s.copy (nodePath = node +: s.nodePath) }) diff --git a/src/main/scala/tilelink/Nodes.scala b/src/main/scala/tilelink/Nodes.scala index 499b89cb..be5281e7 100644 --- a/src/main/scala/tilelink/Nodes.scala +++ b/src/main/scala/tilelink/Nodes.scala @@ -74,17 +74,13 @@ abstract class TLCustomNode( // Asynchronous crossings -object TLAsyncImp extends NodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncEdgeParameters, TLAsyncBundle] +object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { - def edgeO(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo): TLAsyncEdgeParameters = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) - def edgeI(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo): TLAsyncEdgeParameters = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) - - def bundleO(eo: TLAsyncEdgeParameters): TLAsyncBundle = new TLAsyncBundle(eo.bundle) - def bundleI(ei: TLAsyncEdgeParameters): TLAsyncBundle = new TLAsyncBundle(ei.bundle) + def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo): TLAsyncEdgeParameters = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) + def bundle(e: TLAsyncEdgeParameters): TLAsyncBundle = new TLAsyncBundle(e.bundle) def colour = "#ff0000" // red - override def labelI(ei: TLAsyncEdgeParameters) = ei.manager.depth.toString - override def labelO(eo: TLAsyncEdgeParameters) = eo.manager.depth.toString + override def label(e: TLAsyncEdgeParameters) = e.manager.depth.toString override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.copy(clients = pd.base.clients.map { c => c.copy (nodePath = node +: c.nodePath) })) @@ -113,13 +109,10 @@ case class TLAsyncSinkNode(depth: Int, sync: Int)(implicit valName: ValName) // Rationally related crossings -object TLRationalImp extends NodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalEdgeParameters, TLRationalBundle] +object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { - def edgeO(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo): TLRationalEdgeParameters = TLRationalEdgeParameters(pd, pu, p, sourceInfo) - def edgeI(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo): TLRationalEdgeParameters = TLRationalEdgeParameters(pd, pu, p, sourceInfo) - - def bundleO(eo: TLRationalEdgeParameters): TLRationalBundle = new TLRationalBundle(eo.bundle) - def bundleI(ei: TLRationalEdgeParameters): TLRationalBundle = new TLRationalBundle(ei.bundle) + def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo): TLRationalEdgeParameters = TLRationalEdgeParameters(pd, pu, p, sourceInfo) + def bundle(e: TLRationalEdgeParameters): TLRationalBundle = new TLRationalBundle(e.bundle) def colour = "#00ff00" // green