diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala index ede8679c..15ee0920 100644 --- a/rocket/src/main/scala/fpu.scala +++ b/rocket/src/main/scala/fpu.scala @@ -386,7 +386,8 @@ class FPU extends CoreModule when (load_wb) { regfile(load_wb_tag) := load_wb_data_recoded if (EnableCommitLog) { - printf ("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + UInt(32), load_wb_data) + printf ("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + UInt(32), + Mux(load_wb_single, load_wb_data(31,0), load_wb_data)) } } @@ -492,7 +493,7 @@ class FPU extends CoreModule val wdata_unrec_d = hardfloat.recodedFloatNToFloatN(wdata(64,0), 52, 12) val wb_single = (winfo(0) >> 5)(0) printf ("f%d p%d 0x%x\n", waddr, waddr+ UInt(32), - Mux(wb_single, Cat(Fill(32, wdata_unrec_s(31)), wdata_unrec_s), wdata_unrec_d)) + Mux(wb_single, Cat(UInt(0,32), wdata_unrec_s), wdata_unrec_d)) } } diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala index 8b6e3e8f..9a336705 100644 --- a/rocket/src/main/scala/rocket.scala +++ b/rocket/src/main/scala/rocket.scala @@ -43,7 +43,9 @@ abstract trait CoreParameters extends UsesParameters { val coreMaxAddrBits = math.max(ppnBits,vpnBits+1) + pgIdxBits val vaddrBitsExtended = vaddrBits + (vaddrBits < xLen).toInt - val EnableCommitLog = true + // Print out log of committed instructions and their writeback values. + // Requires post-processing due to out-of-order writebacks. + val EnableCommitLog = false if(params(FastLoadByte)) require(params(FastLoadWord)) } @@ -514,12 +516,11 @@ class Rocket extends CoreModule .elsewhen (wxd && rd != UInt(0) && !has_data) { printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", priv, pc, inst, rd, rd) } - .otherwise { // !wxd || (wxd && rd == 0) + .otherwise { printf ("%d 0x%x (0x%x)\n", priv, pc, inst) } } - // ll write data when (ll_wen && rf_waddr != UInt(0)) { printf ("x%d p%d 0x%x\n", rf_waddr, rf_waddr, rf_wdata) }